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* Whitespace removal.Ralf Corsepius2009-12-042-20/+20
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* 2009-02-12 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2009-02-121-1/+1
| | | | | * cpu.c, rtems/score/cpu.h: Change prototype of IDLE thread to consistently return void * and take a uintptr_t argument.
* 2009-02-11 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2009-02-111-20/+1
| | | | | | * cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and passing address of _Thread_Dispatch to _CPU_Initialize. Clean up comments.
* #include <stdint.h> instead of <rtems/stdint.h>.Ralf Corsepius2008-12-111-1/+1
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* 2008-09-11 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2008-09-111-6/+6
| | | | | * rtems/score/types.h: Do not define boolean, single_precision, double_precision unless RTEMS_DEPRECATED_TYPES is given.
* Include stdbool.h. Use bool as base-type for boolean.Ralf Corsepius2008-08-211-1/+2
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* 2008-07-31 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2008-07-311-1/+1
| | | | * cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
* 2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2008-06-051-1/+13
| | | | | | | | * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting parameter to indicate that the port uses the Simple Vectored Interrupt model or the Programmable Interrupt Controller Model. The PIC model is implemented primarily in the BSP and it is responsible for all memory allocation.
* 2008-06-04 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2008-06-041-1/+1
| | | | | | * rtems/score/cpu.h: Use a constant for CPU_STACK_MINIMUM_SIZE so it can be used in cpp expressions. Using sizeof() requires actually compiling the file.
* 2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2007-12-171-0/+3
| | | | * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.
* 2007-12-04 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2007-12-041-11/+0
| | | | | | * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU Table to Configuration Table. Eliminate CPU Table from all ports. Delete references to CPU Table in all forms.
* 2007-12-03 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2007-12-031-10/+0
| | | | | | | | | * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to the Configuration Table. This included pretasking_hook, predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace, extra_mpci_receive_server_stack, stack_allocate_hook, and stack_free_hook. As a side-effect of this effort some multiprocessing code was made conditional and some style clean up occurred.
* 2007-11-26 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2007-11-261-15/+0
| | | | | | * rtems/score/cpu.h: Eliminate the clicks_per_microsecond field in the MIPS CPU Table and define another mechanism for drivers to obtain this information.
* 2007-08-04 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2007-08-041-3/+3
| | | | | * score/cpu/mips/rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
* 2007-05-09 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2007-05-091-2/+0
| | | | * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
* Use Context_Control_fp* instead of void* for fp_contexts.Ralf Corsepius2007-04-171-3/+3
| | | | Eliminate evil casts.
* 2006-11-17 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2006-11-171-4/+0
| | | | * rtems/score/types.h: Remove unsigned64, signed64.
* B.Robinson MIPS patchGreg Menke2006-06-081-6/+16
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* 2006-03-17 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2006-03-171-0/+9
| | | | | * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__. (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
* 2006-01-16 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2006-01-161-5/+4
| | | | | | * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. As a side-effect, grammar and spelling errors were corrected, spacing errors were address, and some variable names were improved.
* 2005-11-18 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2005-11-181-1/+1
| | | | * rtems/score/cpu.h: Eliminate use of unsigned32.
* 2005-11-08 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-11-081-2/+2
| | | | * rtems/score/types.h: Eliminate unsigned16, unsigned32.
* 2005-02-04 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-02-041-1/+1
| | | | | * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h: Header guards cleanup.
* New header guard.Ralf Corsepius2005-01-283-6/+6
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* 2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-01-241-6/+0
| | | | | * rtems/score/types.h: Remove signed8, signed16, signed32, unsigned8, unsigned16, unsigned32.
* 2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-01-241-2/+2
| | | | * rtems/score/cpu.h: *_swap_u32( uint32_t ).
* 2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-01-241-0/+2
| | | | * rtems/score/types.h: #include <rtems/stdint.h>.
* 2005-01-07 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2005-01-071-2/+0
| | | | * rtems/score/cpu.h: Remove warnings.
* PR 730Greg Menke2004-12-062-14/+40
| | | | | * cpu_asm.S: Collected PR 601 changes for commit to cvshead for rtems-4.7
* Cosmetics.Ralf Corsepius2004-11-212-2/+0
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* 2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2004-11-211-2/+2
| | | | | * rtems/score/types.h: Use __rtems_score_types_h as preprocessor guard.
* 2004-10-02 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-11-023-4/+14
| | | | | | * rtems/score/cpu.h: Add doxygen preamble. * rtems/score/mips.h: Add doxygen preamble. * rtems/score/types.h: Add doxygen preamble.
* 2004-09-29 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2004-09-291-4/+1
| | | | * rtems/score/cpu.h: i960 obsoleted and all references removed.
* 2004-04-03 Art Ferrer <arturo.b.ferrer@nasa.gov>Joel Sherrill2004-04-031-0/+1
| | | | | | | PR 598/bsps * cpu_asm.S, rtems/score/cpu.h: Add save of floating point status/control register on context switches. Missing this register was causing intermittent floating point errors.
* 2004-04-02 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-04-031-1/+1
| | | | | | | | * Makefile.am: Install iregdefs.h and idtcpu.h to $(includedir)/rtems/mips. * cpu_asm.S: Include <rtems/mips/iregdef.h> instead of <iregdef.h>. * rtems/score/mips.h, cpu_asm.S: Include <rtems/mips/idtcpu.h> instead of <idtcpu.h>.
* 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-03-301-19/+19
| | | | * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
* Unused.Ralf Corsepius2004-03-081-2/+0
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* 2004-01-07 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2004-01-071-1/+0
| | | | * rtems/score/mips.h: Removed junk revision line.
* 2003-09-26 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2003-09-261-7/+0
| | | | | * rtems/score/cpu.h: Obsoleting HP PA-RISC port and removing all references.
* 2003-09-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2003-09-043-3/+3
| | | | | * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h: URL for license changed.
* 2001-04-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-04-031-1/+1
| | | | | | | * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. * rtems/score/mipstypes.h: Removed. * rtems/score/types.h: New file via CVS magic. * Makefile.am, rtems/score/cpu.h: Account for name change.
* 2002-03-13 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-03-151-22/+26
| | | | | | * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug. * rtems/score/cpu.h: Fixed register numbering in comments and made interrupt enable/disable more robust.
* 2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-03-082-1/+73
| | | | | | | | | | | | * cpu_asm.S: Added support for the debug exception vector, cleaned up the exception processing & exception return stuff. Re-added EPC in the task context structure so the gdb stub will know where a thread is executing. Should've left it there in the first place... * idtcpu.h: Added support for the debug exception vector. * cpu.c: Added ___exceptionTaskStack to hold a pointer to the stack frame in an interrupt so context switch code can get the userspace EPC when scheduling. * rtems/score/cpu.h: Re-added EPC to the task context.
* 2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-03-011-3/+16
| | | | | | | | | | | | | | | | * cpu_asm.S: Fixed exception return address, modified FP context switch so FPU is properly enabled and also doesn't screw up the exception FP handling. * idtcpu.h: Added C0_TAR, the MIPS target address register used for returning from exceptions. * iregdef.h: Added R_TAR to the stack frame so the target address can be saved on a per-exception basis. The new entry is past the end of the frame gdb cares about, so doesn't affect gdb or cpu.h stuff. * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it to obtain FPU defines without systax errors generated by the C defintions. * cpu.c: Improved interrupt level saves & restores.
* 2002-02-08 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-02-081-101/+105
| | | | | * iregdef.h, rtems/score/cpu.h: Reordered register in the exception stack frame to better match gdb's expectations.
* 2001-02-05 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-02-051-11/+132
| | | | | | | | | * cpu_asm.S: Enhanced to save/restore more registers on exceptions. * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every register individually and document when it is saved. * idtcpu.h: Added constants for the coprocessor 1 registers revision and status.
* 2001-02-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-02-041-1/+1
| | | | | * rtems/score/cpu.h: IDLE task should not be FP. This was a mistake in the previous patch that has now been confirmed.
* 2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-02-011-19/+44
| | | | | | | | | * cpu.c: Enhancements and fixes for modifying the SR when changing the interrupt level. * cpu_asm.S: Fixed handling of FP enable bit so it is properly managed on a per-task basis, improved handling of interrupt levels, and made deferred FP contexts work on the MIPS. * rtems/score/cpu.h: Modified to support above changes.
* 2001-11-28 Joel Sherrill <joel@OARcorp.com>,Joel Sherrill2001-11-281-0/+7
| | | | | | | This was tracked as PR91. * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which is used to specify if the port uses the standard macro for this (FALSE). A TRUE setting indicates the port provides its own implementation.
* 2000-05-24 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-05-241-7/+38
| | | | | | | * rtems/score/mips.h: Added constants for MIPS exception numbers. All exceptions should be given low numbers and thus can be installed and processed in a uniform manner. Variances between various MIPS ISA levels were not accounted for.
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