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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-03-08 16:24:48 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-03-08 16:24:48 +0000 |
commit | 8264d230a9f2f0312aec4c0fa6503139cea61d7c (patch) | |
tree | 3b39b52e75a369cc4cdf491bf0c5d39332880a22 /cpukit/score/cpu/mips/rtems/score | |
parent | 2002-03-06 Victor V. Vengerov <vvv@oktet.ru> (diff) | |
download | rtems-8264d230a9f2f0312aec4c0fa6503139cea61d7c.tar.bz2 |
2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Added support for the debug exception vector, cleaned
up the exception processing & exception return stuff. Re-added
EPC in the task context structure so the gdb stub will know where
a thread is executing. Should've left it there in the first place...
* idtcpu.h: Added support for the debug exception vector.
* cpu.c: Added ___exceptionTaskStack to hold a pointer to the
stack frame in an interrupt so context switch code can get the
userspace EPC when scheduling.
* rtems/score/cpu.h: Re-added EPC to the task context.
Diffstat (limited to 'cpukit/score/cpu/mips/rtems/score')
-rw-r--r-- | cpukit/score/cpu/mips/rtems/score/cpu.h | 2 | ||||
-rw-r--r-- | cpukit/score/cpu/mips/rtems/score/mips.h | 72 |
2 files changed, 73 insertions, 1 deletions
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h index d2a29ed4f0..ed87991c3c 100644 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ b/cpukit/score/cpu/mips/rtems/score/cpu.h @@ -385,7 +385,7 @@ typedef struct { __MIPS_REGISTER_TYPE fp; __MIPS_REGISTER_TYPE ra; __MIPS_REGISTER_TYPE c0_sr; -/* __MIPS_REGISTER_TYPE c0_epc; */ + __MIPS_REGISTER_TYPE c0_epc; } Context_Control; /* WARNING: If this structure is modified, the constants in cpu.h diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h index 216e307ff7..ea5a4b545d 100644 --- a/cpukit/score/cpu/mips/rtems/score/mips.h +++ b/cpukit/score/cpu/mips/rtems/score/mips.h @@ -140,6 +140,78 @@ extern "C" { } while (0) + + +/* + * Access the Debug Cache Invalidate Control register + */ + +#define mips_get_dcic( _x ) \ + do { \ + asm volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \ + } while (0) + + +#define mips_set_dcic( _x ) \ + do { \ + register unsigned int __x = (_x); \ + asm volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \ + } while (0) + + + + +/* + * Access the Breakpoint Program Counter & Mask registers + * (_x for BPC, _y for mask) + */ + +#define mips_get_bpcrm( _x, _y ) \ + do { \ + asm volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \ + asm volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \ + } while (0) + + +#define mips_set_bpcrm( _x, _y ) \ + do { \ + register unsigned int __x = (_x); \ + register unsigned int __y = (_y); \ + asm volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \ + asm volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \ + } while (0) + + + + + + +/* + * Access the Breakpoint Data Address & Mask registers + * (_x for BDA, _y for mask) + */ + +#define mips_get_bdarm( _x, _y ) \ + do { \ + asm volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \ + asm volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \ + } while (0) + + +#define mips_set_bdarm( _x, _y ) \ + do { \ + register unsigned int __x = (_x); \ + register unsigned int __y = (_y); \ + asm volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \ + asm volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \ + } while (0) + + + + + + + /* * Access FCR31 */ |