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* Just "cc" in the clobbered register list for interrupt enable/disable/flashEric Norum2006-02-281-5/+9
| | | | | operations. The "memory" barrier will move the the generic interrupt enable/disable/flash macros.
* 2006-01-16 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2006-01-161-2/+2
| | | | | | * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. As a side-effect, grammar and spelling errors were corrected, spacing errors were address, and some variable names were improved.
* 2005-11-08 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-11-081-2/+2
| | | | * rtems/score/types.h: Eliminate unsigned16, unsigned32.
* 2005-10-27 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-10-271-7/+1
| | | | | * rtems/asm.h: Remove private version of CONCAT macros. Include <rtems/concat.h> instead.
* 2005-06-07 Brett Swimley <brett.swimley@aedbozeman.com>Joel Sherrill2005-06-072-6/+6
| | | | | PR 803/patch * rtems/score/cpu.h, rtems/score/m68k.h: Correct definition of _VBR.
* 2005-05-20 Chris Johns <chrisj@rtems.org>Joel Sherrill2005-05-202-2/+2
| | | | * rtems/score/cpu.h, rtems/score/m68k.h: Change declaration of _VBR.
* 2005-05-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2005-05-041-1/+1
| | | | * rtems/score/m68k.h: Change _ColdFire_VBR to _VBR.
* 2005-05-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2005-05-032-3/+3
| | | | | * rtems/score/cpu.h: Change definition of _VBR to a simple pointer. * rtems/score/m68k.h: Remove use of _Coldfire_VBR.
* 2005-02-04 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-02-045-12/+12
| | | | | * rtems/m68k/m68302.h, rtems/m68k/m68360.h, rtems/m68k/qsm.h, rtems/m68k/sim.h, rtems/score/m68k.h: Header guards cleanup.
* ColdFire ISA A+ instructions.Eric Norum2005-01-282-8/+34
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* New header guard.Ralf Corsepius2005-01-284-8/+8
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* 2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-01-241-6/+0
| | | | | * rtems/score/types.h: Remove signed8, signed16, signed32, unsigned8, unsigned16, unsigned32.
* 2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-01-241-5/+5
| | | | * rtems/score/m68k.h: *_swap_u32( uint32_t ).
* 2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-01-241-5/+5
| | | | * rtems/score/m68k.h: *_swap_u16( uint16_t ).
* 2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-01-241-0/+2
| | | | * rtems/score/types.h: #include <rtems/stdint.h>.
* Cosmetics.Ralf Corsepius2004-11-215-5/+0
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* 2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2004-11-211-2/+2
| | | | | * rtems/score/types.h: Use __rtems_score_types_h as preprocessor guard.
* 2004-11-12 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2004-11-211-3/+5
| | | | * asm.h: Add doxygen preamble.
* 2004-11-19 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-11-191-1/+1
| | | | | * rtems/score/m68k.h: Use (defined(__mc68020__) && !defined(__mcpu32__)) instead of defined(__mc68020__) to reflect GCC-3.4's expectations.
* 2004-10-02 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-11-023-6/+15
| | | | | | * rtems/score/cpu.h: Add doxygen preamble. * rtems/score/m68k.h: Add doxygen preamble. * rtems/score/types.h: Add doxygen preamble.
* 2004-07-25 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2004-07-251-0/+1
| | | | | * rtems/score/m68k.h: Add include of <stdint.h> for uint32_t used by endian swapping routines.
* 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-03-303-172/+172
| | | | | * cpu.c, m68302.h, rtems/score/cpu.h, rtems/score/m68k.h: Convert to using c99 fixed size types.
* Unused.Ralf Corsepius2004-03-082-4/+0
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* 2004-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Ralf Corsepius2004-01-301-4/+5
| | | | | PR 561/rtems * asm.h: Add CONCAT0, EVAL. Let SYM and REG use CONCAT0 and EVAL.
* 2004-01-07 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2004-01-072-4/+2
| | | | | * qsm.h, sim.h: Remove efi68k and efi332 references as they are no longer in the tree.
* 2003-09-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2003-09-043-3/+3
| | | | | * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/m68k.h, rtems/score/types.h: URL for license changed.
* 2003-02-06 Ilya Alexeev <ilya@continuum.ru>Joel Sherrill2003-02-061-2/+2
| | | | | * m68360.h: Correct the order of fields in the ethernet structure to account for the typo in MC68360UM (page 7-248).
* 2002-08-14 Brett Swimley <brett.swimley@aedinc.net>Joel Sherrill2002-08-141-1/+12
| | | | | | | | | | * cpu_asm.S: Per PR267, the _ISR_Handler() function never was modifying _ISR_Nest_level, and _Watchdog_Insert() requires this variable to be modified to determine if an interrupt may have modified the watchdog chain. Prior to modifying _ISR_Handler(), I had a test that would fail if _ISR_Flash was not commented out in _Watchdog_Insert(). After this modification was made, my test ran flawlessly.
* 2002-05-28 Chris Johns <ccj@acm.org>Joel Sherrill2002-05-281-1/+1
| | | | | * rtems/score/m68k.h: Per PR227, mc68060 does not require FPSP since it is now multilib'ed.
* 2001-04-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-04-032-2/+2
| | | | | | * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. * include/rtems/score/ispsh7750.h, score/ispsh7750.c: Account for name change.
* 2002-03-15 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2002-03-151-1/+1
| | | | * rtems/score/m68k.h: m68k_swap_u32 fix typo.
* 2002-03-06 Victor V. Vengerov <vvv@oktet.ru>Joel Sherrill2002-03-061-0/+33
| | | | | | * rtems/score/m68k.h [M68K_COLDFIRE_ARCH] (CPU_swap_u16, CPU_swap_u32): Generic implementation of endian swap primitives added for Coldfire family.
* 2001-11-28 Joel Sherrill <joel@OARcorp.com>,Joel Sherrill2001-11-281-0/+7
| | | | | | | This was tracked as PR91. * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which is used to specify if the port uses the standard macro for this (FALSE). A TRUE setting indicates the port provides its own implementation.
* 2001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-031-0/+3
| | | | | | * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). * cpu_asm.S: Modify to properly dereference _ISR_Vector_table now that it is dynamically allocated.
* 2000-10-19 Antti P Miettinen <anmietti@trshp.ntc.nokia.com>Joel Sherrill2000-10-192-6/+16
| | | | | * rtems/score/cpu.h: define CPU_Exception_frame for rdbg. * m68302.h: Make buffer pointer in m302_SCC_bd volatile.
* 2000-10-12 John S Gwynne <jgwynne@mrcday.com>Joel Sherrill2000-10-121-5/+4
| | | | | | | | | | | | | | * sim.h: These changes enable RTEMS to automatically generate the ram_init file used by gdb with the BDM patches. The 332 has on-board chip select lines (for RAM and FLASH) that must be configured before use of these peripherals. These patches parse data from start.c where the chip select lines are configured in the runtime executable and automatically generates the gdb initialization file using the same settings. A great time saver. A similar file, ram_init_FW (flash writable), is also generated that the flash programming tool uses. * BSP/start/start.c: Must be modified to support above. * BSP/start/ram_init.ld, BSP/start/ram_init.sed: New files.
* Patch rtems-rc-20000711-1-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2000-07-111-1/+1
| | | | | | | | | that decouples exec/ for the sh, m68k and i960 from targopts.h. NOTE: The change to system.h is a hack to enable cpuopts.h for some targets, but keep using targopts.h for others - I know it does *not* work for sparc, mips, i386 and ppc. This will have to be addressed as work continues on multilibing.
* Moved i386 and m68k cache management code to libcpu. EverythingJoel Sherrill2000-06-131-211/+0
| | | | | | now is an implementation of the prototypes in rtems/rtems/cache.h. The libcpu/i386/wrapup directory is no longer needed. The PowerPC needs this done to it.
* Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine GauthierJoel Sherrill2000-06-121-8/+231
| | | | | | | | | | | | | | | <charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart <Darlene.Stewart@nrc.ca> to add support for a number of very significant things: + BSPs for many variations on the Motorola MBX8xx board series + Cache Manager including initial support for m68040 and PowerPC + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use same code base. + Rework of eth_comm BSP to utiltize above. John reports this works on the 821 and 860
* Merged from 4.5.0-beta3aJoel Sherrill2000-06-123-11/+9
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* Patch rtems-rc-4.5.0-13-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>.Joel Sherrill2000-04-132-0/+4
| | | | adds .cvsignore.
* Increased stack size to 4K per Eric Norum.Joel Sherrill2000-01-031-1/+1
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* Patch from Jepsen Hans Peter <hans_peter_jepsen@Danfoss.com> toJoel Sherrill1999-12-131-1/+1
| | | | use correct ifdef conditional (__GNUC__ not __GCC__).
* Changed name of W, X, and Y macros for fields in the ClockJoel Sherrill1999-11-221-9/+9
| | | | Synthesizer Control Register to remove use of single letter names.
* Updated copyright notice.Joel Sherrill1999-11-173-6/+3
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* This is another pass at making sure that nothing outside the BSPJoel Sherrill1999-11-051-0/+12
| | | | | | | | | | | | unnecessarily uses any variables defined by the BSP. On this sweep, use of BSP_Configuration and Cpu_table was eliminated. A significant part of this modification was the addition of macros to access fields in the RTEMS configuration structures. This is necessary to strengthen the division between the BSP independent parts of RTEMS and the BSPs themselves. This started after comments and analysis by Ralf Corsepius <corsepiu@faw.uni-ulm.de>.
* Patch from Charles-Antoine Gauthier <charles.gauthier@iit.nrc.ca>Joel Sherrill1999-07-291-1/+1
| | | | | to correct a typo CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES was actually typed in as CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
* Moved back up in tree.Joel Sherrill1999-02-194-0/+2101
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* Moved asm.h back up in tree.Joel Sherrill1999-02-191-0/+144
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* Moved to proper rtems/scoreJoel Sherrill1999-02-195-2245/+0
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