| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
| |
Use de-facto standard BYTE_ORDER instead.
Close #2803.
|
|
|
|
|
|
|
|
|
|
|
|
| |
On SMP configurations, it is a fatal error to call blocking operating
system with interrupts disabled, since this prevents delivery of
inter-processor interrupts. This could lead to executing threads which
are not allowed to execute resulting in undefined behaviour.
The ARM Cortex-M port has a similar problem, since the interrupt state
is not a part of the thread context.
Update #2811.
|
|
|
|
|
|
|
| |
In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates
a level parameter and returns a boolean value.
Update #2811.
|
|
|
|
| |
Update #2808.
|
|
|
|
|
| |
Move CPU_PER_CPU_CONTROL_SIZE and the optional CPU_Per_CPU_control to
<rtems/score/cpuimpl.h> to hide it from <rtems.h>.
|
|
|
|
| |
The thread dispatch inline option is no longer used.
|
|
|
|
|
|
|
| |
Only use CPU_Per_CPU_control if it contains at least one filed. In GNU
C empty structures have a size of zero. In C++ structures have a
non-zero size. In case CPU_PER_CPU_CONTROL_SIZE is defined to zero,
then this structure is not used anymore.
|
|
|
|
|
|
| |
Rename __log2table into _Bitfield_Leading_zeros since it acually returns
the count of leading zeros of an 8-bit integer. The value for zero is a
bit odd. Provide it unconditionally.
|
| |
|
|
|
|
| |
Maximum number of processors of all systems supported by this CPU port.
|
|
|
|
| |
Update #2559.
|
|
|
|
|
| |
Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The
actual processor may use no cache or a smaller cache line size.
|
|
|
|
| |
Update #2271.
|
| |
|
| |
|
| |
|
|
|
|
|
|
|
|
|
| |
Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.
This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.
|
|
|
|
| |
Rename Priority_bit_map_Control in Priority_bit_map_Word.
|
| |
|
|
|
|
|
|
|
|
|
| |
Add a CPU counter interface to allow access to a free-running counter.
It is useful to measure short time intervals. This can be used for
example to enable profiling of critical low-level functions.
Add two busy wait functions rtems_counter_delay_ticks() and
rtems_counter_delay_nanoseconds() implemented via the CPU counter.
|
|
|
|
|
| |
Tested and implemented on ARM, m68k, PowerPC and SPARC. Other
architectures need more work.
|
|
|
|
| |
Add CPU port specific per-CPU control.
|
| |
|
|
|
|
|
| |
This is the result of a sed script which converts all uses
of @{ into a consistent form.
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add CPU port type CPU_Exception_frame and function
_CPU_Exception_frame_print().
The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh,
sparc64, and v850 use an empty default implementation of
_CPU_Exception_frame_print().
Add rtems_exception_frame and rtems_exception_frame_print().
Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal()
with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc,
and sparc for unexpected exceptions.
Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the
BSP_PRINT_EXCEPTION_CONTEXT define used in the default
bsp_fatal_extension().
Add test sptests/spfatal26.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add and use new CPU port define CPU_SIZEOF_POINTER. It must be an
integer literal that can be used by the assembler. This value will be
used to calculate offsets of structure members. These offsets will be
used in assembler code.
The size of a pointer is part of the application binary interface (ABI)
and thus independent of the actual programming language. The compiler
will provide defines to determine the current ABI. We use these defines
to select the appropriate CPU_SIZEOF_POINTER value.
Static assertions in the new file "cpukit/score/src/percpuasm.c" will
ensure that the value of CPU_SIZEOF_POINTER is consistent with the
current compiler settings. Also the offset values used by assembler
code are verfied.
|
|
|
|
|
|
|
|
|
|
|
|
| |
Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
|
|
|
|
|
|
| |
PR 1956/cpukit
* rtems/score/cpu.h: Correct multiple alignment constants. Improve
comments.
|
|
|
|
|
| |
PR 1955/cpukit
* rtems/score/cpu.h: Convert CPU_swap_u16 into a static inline.
|
|
|
|
|
| |
PR 1914/cpukit
* rtems/score/cpu.h: Select timestamp implementation.
|
|
|
|
|
|
| |
* rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to
_CPU_Context_restore() because it does not return. Telling GCC this
avoids generation of dead code.
|
|
|
|
|
|
| |
PR 1697/cpukit
* rtems/score/cpu.h: lm32 really needs aligned stack. Recent changes
highlighted that this macro was incorrect.
|
|
|
|
|
|
|
|
|
|
|
| |
PR 1635/cpukit
* rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority
handling, to isolate the bitmap implementation of priorities in the
supercore so that priority management is a little more modular. This
change is in anticipation of scheduler implementations that can
select how they manage tracking priority levels / finding the highest
priority ready task. Note that most of the changes here are simple
renaming, to clarify the use of the bitmap-based priority management.
|
|
|
|
|
| |
* rtems/score/cpu.h: Include <rtems/score/types.h> first.
* rtems/score/types.h: Use <rtems/score/basedefs.h> header file.
|
|
|
|
|
|
|
|
| |
PR 1573/cpukit
* irq.c, rtems/score/cpu.h: Add a per cpu data structure which contains
the information required by RTEMS for each CPU core. This
encapsulates information such as thread executing, heir, idle and
dispatch needed.
|
|
|
|
| |
* rtems/score/cpu.h: Remove warning in _CPU_Context_Initialize.
|
|
|
|
| |
* rtems/score/cpu.h: Make _gp global.
|
| |
|
|
|
|
| |
* cpu_asm.S, irq.c, rtems/score/cpu.h: Add lm32 gdb stub support.
|
|
|
|
|
|
|
|
|
|
|
|
| |
* cpu.h: corrected the registers in Context_Control and
in CPU_Interrupt_frame to correspond to the saved frame in cpu_asm.S
Also switched on CPU_ISR_PASSES_FRAME_POINTER.
* cpu_asm.S: Moved the restore part of _CPU_Context_switch for
easier reading. Fixed _CPU_Context_restore, it now moves the
argument and branches to a label in _CPU_Context_switch. Removed
unnecessary saves of registers in context switch and irq handling.
Rewrote irq code to call the C helper. Added some documentation
* irq.c: New file derived from c4x and nios2.
|
|
|
|
|
| |
* cpu.c, rtems/score/cpu.h: Change prototype of IDLE thread to
consistently return void * and take a uintptr_t argument.
|
|
|
|
|
|
| |
* cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and
passing address of _Thread_Dispatch to _CPU_Initialize. Clean up
comments.
|
|
* ChangeLog, Makefile.am, cpu.c, cpu_asm.S, preinstall.am, rtems/asm.h,
rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/lm32.h,
rtems/score/types.h: New files.
|