| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
| |
Add CPU port define for the interrupt stack alignment. The alignment
should take the stack ABI and the cache line size into account.
Update #3459.
|
|
|
|
|
|
|
|
|
|
| |
Use the standard ARMv7-M systick module for the ARMv7-M CPU counter
instead of DWT counter since the DWT counter is affected by power saving
states.
Use an inline function for _CPU_Counter_difference() for all ARM BSPs.
Update #3456.
|
|
|
|
|
|
|
|
|
|
| |
Add rtems_counter_frequency() API function. Use it to initialize the
counter value converter via the new system initialization step
(RTEMS_SYSINIT_CPU_COUNTER). This decouples the counter implementation
and the counter converter. It avoids an unnecessary pull in of the
64-bit integer division from libgcc.
Update #3456.
|
| |
|
|
|
|
| |
Closes #3305.
|
|
|
|
| |
Updates #3327.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.
This has at least seven problems:
* The make preinstall step itself needs time and disk space.
* Errors in header files show up in the build tree copy. This makes it
hard for editors to open the right file to fix the error.
* There is no clear relationship between source and build tree header
files. This makes an audit of the build process difficult.
* The visibility of all header files in the build tree makes it
difficult to enforce API barriers. For example it is discouraged to
use BSP-specifics in the cpukit.
* An introduction of a new build system is difficult.
* Include paths specified by the -B option are system headers. This
may suppress warnings.
* The parallel build had sporadic failures on some hosts.
This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.
The new cpukit include directories are:
* cpukit/include
* cpukit/score/cpu/@RTEMS_CPU@/include
* cpukit/libnetworking
The new BSP include directories are:
* bsps/include
* bsps/@RTEMS_CPU@/include
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include
There are build tree include directories for generated files.
The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.
The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.
Update #3254.
|
|
|
|
| |
Update #3254.
|
|
|
|
| |
Update #3093.
|
|
|
|
| |
Update #3093.
|
|
|
|
|
|
|
|
|
|
|
|
| |
Right after a "msr basepri_max, %[basepri]" instruction an interrupt
service may still take place (observed at least on Cortex-M7). However,
pendable service calls that are activated during this interrupt service
may be delayed until interrupts are enable again. The
_ARMV7M_Pendable_service_call() did not check that a thread dispatch is
allowed. Move this test from _ARMV7M_Interrupt_service_leave() to
_ARMV7M_Pendable_service_call().
Update #3060.
|
|
|
|
|
|
| |
There is no need to save the thread pointer in _CPU_Context_switch()
since it is a thread invariant. It is initialized once in
_CPU_Context_Initialize().
|
|
|
|
| |
Update #2751.
|
|
|
|
|
|
|
|
|
| |
Set CPU_ENABLE_ROBUST_THREAD_DISPATCH to TRUE. In this case the
interrupts are always enabled during a context switch even after
interrupt processing (see #2751). Remove the CPSR from the context
control since it contains only volatile bits.
Close #2954.
|
|
|
|
| |
Do not touch the FPSCR[QC] bit since this is DNM/RAZ on Cortex-R4.
|
| |
|
|
|
|
|
|
|
|
|
| |
It is necessary to enable the DWT using a special initialization
sequence before the CYCCNT can be enabled. See for example the
RESET_CYCLE_COUNTER in libbsp/arm/atsam/utils/utility.h.
Note that this problem only occurs if no debugger is connected. A
debugger most likely already enables the necessary module.
|
|
|
|
|
|
|
|
|
|
| |
Since the FP area pointer is passed by reference in
_CPU_Context_Initialize_fp() the optional FP area adjustment via
_CPU_Context_Fp_start() is superfluous. It is also wrong with respect
to memory management, e.g. pointer passed to _Workspace_Free() may be
not the one returned by _Workspace_Allocate().
Close #1400.
|
| |
|
|
|
|
|
|
| |
Use de-facto standard BYTE_ORDER instead.
Close #2803.
|
|
|
|
| |
Update #2751.
|
|
|
|
| |
Update #2811.
|
|
|
|
|
|
|
|
|
|
|
|
| |
On SMP configurations, it is a fatal error to call blocking operating
system with interrupts disabled, since this prevents delivery of
inter-processor interrupts. This could lead to executing threads which
are not allowed to execute resulting in undefined behaviour.
The ARM Cortex-M port has a similar problem, since the interrupt state
is not a part of the thread context.
Update #2811.
|
|
|
|
|
|
|
| |
Use the right register to determine if a thread dispatch is allowed and
necessary.
Update #2751.
|
|
|
|
|
|
|
| |
We cannot use the MRS or MSR instructions in Thumb-1 mode. Stay in ARM
mode for the Thumb-1 targets during interrupt low-level processing.
Update #2751.
|
|
|
|
| |
Close #2816.
|
|
|
|
|
|
|
| |
In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates
a level parameter and returns a boolean value.
Update #2811.
|
|
|
|
| |
Update #2751.
|
|
|
|
|
| |
Move profiling code closer to bsp_interrupt_disable() to allow re-use of
r9 later.
|
| |
|
|
|
|
|
|
|
|
|
| |
Use a processor-specific interrupt frame during context switches in case
the executing thread is longer executes on the processor and the heir
thread is about to start execution. During this period we must not use
a thread stack for interrupt processing.
Update #2809.
|
|
|
|
| |
Update #2809.
|
|
|
|
| |
Update #2808.
|
|
|
|
|
| |
Move CPU_PER_CPU_CONTROL_SIZE and the optional CPU_Per_CPU_control to
<rtems/score/cpuimpl.h> to hide it from <rtems.h>.
|
|
|
|
| |
The thread dispatch inline option is no longer used.
|
|
|
|
|
|
| |
Use the previously unused TPIDRPRW register to get the per-CPU control
of the current processor. This avoids instructions in
GET_SELF_CPU_CONTROL which are not available in Thumb mode.
|
|
|
|
|
|
| |
The aim of this file is to encapsulate CPU port implementation details.
This helps to hide implementation details from <rtems.h> which
indirectly includes <rtems/score/cpu.h>.
|
|
|
|
|
|
|
|
| |
The use of actual cache line max bytes and minimum required alignment
in architecture but not-BSP dependent code could be problematic
because there exists even ARM instruction set implementations
with 128 byte line length and real maximum can be quite problematic
to say. But actually supported ARM BSPs should be OK with these values.
|
|
|
|
|
|
|
| |
Only use CPU_Per_CPU_control if it contains at least one filed. In GNU
C empty structures have a size of zero. In C++ structures have a
non-zero size. In case CPU_PER_CPU_CONTROL_SIZE is defined to zero,
then this structure is not used anymore.
|
| |
|
| |
|
|
|
|
|
| |
Some/many Cortex-A cores have data cache line length 64 bytes and maximum
value has to be used for system structures alignment.
|
|
|
|
|
|
|
|
|
| |
base access.
The main reason for inclusion of minimum hypervisor related defines
is that current ARM boards firmware and loaders (U-boot for example)
start loaded operating system kernel in HYP mode to allow it take
control of virtualization (Linux/KVM for example).
|
|
|
|
|
|
|
|
|
|
| |
The priority bit map can deal with a maximum of 256 priority values
ranging from 0 to 255. Consistently use an unsigned int for
computation, due to the usual integer promotion rules.
Make Priority_bit_map_Word definition architecture-independent and
define it to uint16_t. This was already the case for all architectures
except PowerPC. Adjust the PowerPC bitmap support accordingly.
|
|
|
|
|
|
| |
Rename __log2table into _Bitfield_Leading_zeros since it acually returns
the count of leading zeros of an 8-bit integer. The value for zero is a
bit odd. Provide it unconditionally.
|
| |
|
|
|
|
|
|
|
|
|
| |
Rename _ISR_Disable() into _ISR_Local_disable(). Rename _ISR_Enable()
into _ISR_Local_enable(). Remove _Debug_Is_owner_of_giant().
This is a preparation to remove the Giant lock.
Update #2555.
|
|
|
|
| |
Maximum number of processors of all systems supported by this CPU port.
|
|
|
|
| |
Also add a comment explaining why we use that value.
|
| |
|