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* doxygen: score: Put ARM Co-Processor 15 group in ARMAndreas Dachsberger2019-04-021-3/+3
| | | | Update #3706.
* score: Add ARM CPU architecture groupSebastian Huber2019-03-2610-52/+32
| | | | Update #3706.
* score: Rename ScoreCPU Doxygen groupSebastian Huber2019-03-268-10/+10
| | | | Update #3706.
* Remove superfluous <rtems/system.h> includesSebastian Huber2019-03-142-2/+0
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* cpukit/arm: Correct register definitionJonathan Brandmeyer2019-03-081-2/+2
| | | | | | | | | | | | | | The register definition for the CP15 PMCR (performance monitor control register) has the bits for X (export enable) and D (clock divider enable) backwards. Correct them according to ARMv7-A/R Architecture Reference Manual, Rev C, Section B4.1.117. Consequences: On an implementation that starts off with D set at reset, the clock divider will not be disabled by using RTEMS' definition of the D bit. Tested by using the counter on Xilinx Zynq 7020 to measure some atomic accesses and cache flushing operations.
* bsps/arm: Fix system register for virtual timerKinsey Moore2019-02-221-1/+1
| | | | | | | | | The system register in use for retrieval of the virtual timer value was mistakenly copied from the physical timer value retrieval function. Virtual timer value retrieval should use the same system register as the virtual timer value setter. Close #3699.
* libdl: Fix the support for constructors and desctructors.Chris Johns2019-02-091-20/+52
| | | | | | | - Fix the handling of pending objects. - Add a constructor flags in objects to track then being called. Closes #2921
* arm: Remove use of proc_ptrSebastian Huber2018-11-123-14/+16
| | | | Update #3585.
* build: Include header.am in cpukit/Makefile.amSebastian Huber2018-10-102-24/+11
| | | | | Include all cpukit/*/header.am files in cpukit/Makefile.am. This gets rid of all subtree Makefile.am and the sudirs hack.
* build: Merge score/cpu/*/Makefile.amSebastian Huber2018-10-101-34/+0
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* build: Remove specialized CPPFLAGSSebastian Huber2018-10-091-1/+0
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* score: Remove CPU_PROVIDES_IDLE_THREAD_BODYSebastian Huber2018-10-052-12/+4
| | | | | | | Remove the CPU_PROVIDES_IDLE_THREAD_BODY option to avoid unnecessary conditional compilation. Close #3539.
* score: Remove CPU_PARTITION_ALIGNMENTSebastian Huber2018-08-021-3/+0
| | | | | | | | | | | | | | Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment requirement is defined by the use of Chain_Node (consisting of two pointers) to manage the free chain of partitions. It seems that previously the condition CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node) was true on all CPU ports. Now, we need an additional check. Update #3482.
* score: Add _CPU_Instruction_illegal()Sebastian Huber2018-07-231-0/+5
| | | | | | | | On some architectures/simulators it is difficult to provoke an exception with misaligned or illegal data loads. Use an illegal instruction instead. Update #3433.
* score: Add _CPU_Instruction_no_operation()Sebastian Huber2018-07-201-0/+5
| | | | | This helps to reduce the use of architecture-specific defines throughout the code base.
* score: Move context validation declarationsSebastian Huber2018-07-202-4/+4
| | | | | | | The context validation support functions _CPU_Context_validate() and _CPU_Context_volatile_clobber() are used only by one test program (spcontext01). Move the function declarations to the CPU port implementation header file.
* Rework initialization and interrupt stack supportSebastian Huber2018-06-271-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Statically initialize the interrupt stack area (_Configuration_Interrupt_stack_area_begin, _Configuration_Interrupt_stack_area_end, and _Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the interrupt stack area in a special section ".rtemsstack.interrupt". Let BSPs define the optimal placement of this section in their linker command files (e.g. in a fast on-chip memory). This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the low level initialization code has all information available via global symbols. This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define superfluous, since the interrupt stacks are allocated by confdefs.h for all architectures. There is no need for BSP-specific linker command file magic (except the section placement), see previous ARM linker command file as a bad example. Remove _CPU_Install_interrupt_stack(). Initialize the hardware interrupt stack in _CPU_Initialize() if necessary (e.g. m68k_install_interrupt_stack()). The optional _CPU_Interrupt_stack_setup() is still useful to customize the registration of the interrupt stack area in the per-CPU information. The initialization stack can reuse the interrupt stack, since * interrupts are disabled during the sequential system initialization, and * the boot_card() function does not return. This stack resuse saves memory. Changes per architecture: arm: * Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases. * Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp. bfin: * Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value. lm32, m32c, mips, nios2, riscv, sh, v850: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. m68k: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. powerpc: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. * Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA). sparc: * Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM. Update #3459.
* score: Add CPU_INTERRUPT_STACK_ALIGNMENTSebastian Huber2018-06-271-0/+2
| | | | | | | Add CPU port define for the interrupt stack alignment. The alignment should take the stack ABI and the cache line size into account. Update #3459.
* arm: Simplify CPU counter supportSebastian Huber2018-06-151-2/+5
| | | | | | | | | | Use the standard ARMv7-M systick module for the ARMv7-M CPU counter instead of DWT counter since the DWT counter is affected by power saving states. Use an inline function for _CPU_Counter_difference() for all ARM BSPs. Update #3456.
* Add _CPU_Counter_frequency()Sebastian Huber2018-06-151-0/+2
| | | | | | | | | | Add rtems_counter_frequency() API function. Use it to initialize the counter value converter via the new system initialization step (RTEMS_SYSINIT_CPU_COUNTER). This decouples the counter implementation and the counter converter. It avoids an unnecessary pull in of the 64-bit integer division from libgcc. Update #3456.
* Drop executable permissions on .[ch] filesJoel Sherrill2018-04-301-0/+0
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* Add ARM Paravirtualization supportJoel Sherrill2018-03-134-3/+90
| | | | Closes #3305.
* arm/include/rtems/score/types.h: Eliminate this fileJoel Sherrill2018-03-123-53/+4
| | | | Updates #3327.
* Remove make preinstallChris Johns2018-01-2513-87/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254.
* arm: Move <libcpu/arm-cp15.h> to cpukitSebastian Huber2017-12-133-0/+2272
| | | | Update #3254.
* arm: Use ARM code on Thumb 1 targetsSebastian Huber2017-08-101-1/+1
| | | | Update #3093.
* arm: Validate IT[7:0] bit field of PSRSebastian Huber2017-08-101-1/+25
| | | | Update #3093.
* arm: Fix ARMv7-M interrupt processingSebastian Huber2017-07-042-30/+48
| | | | | | | | | | | | Right after a "msr basepri_max, %[basepri]" instruction an interrupt service may still take place (observed at least on Cortex-M7). However, pendable service calls that are activated during this interrupt service may be delayed until interrupts are enable again. The _ARMV7M_Pendable_service_call() did not check that a thread dispatch is allowed. Move this test from _ARMV7M_Interrupt_service_leave() to _ARMV7M_Pendable_service_call(). Update #3060.
* Simplify TLS support in context switchSebastian Huber2017-06-091-11/+2
| | | | | | There is no need to save the thread pointer in _CPU_Context_switch() since it is a thread invariant. It is initialized once in _CPU_Context_Initialize().
* arm: Fix profiling support of Thumb-1 targetsSebastian Huber2017-05-231-1/+3
| | | | Update #2751.
* arm: Optimize context switchSebastian Huber2017-03-283-78/+55
| | | | | | | | | Set CPU_ENABLE_ROBUST_THREAD_DISPATCH to TRUE. In this case the interrupts are always enabled during a context switch even after interrupt processing (see #2751). Remove the CPSR from the context control since it contains only volatile bits. Close #2954.
* arm: Fix CPU context validation for Cortex-R4Sebastian Huber2017-03-092-7/+3
| | | | Do not touch the FPSCR[QC] bit since this is DNM/RAZ on Cortex-R4.
* arm: Remove legacy execption supportSebastian Huber2017-03-084-301/+0
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* bsps/arm: Fix Cortex-M DWT CPU counter.Christian Mauderer2017-01-301-1/+45
| | | | | | | | | It is necessary to enable the DWT using a special initialization sequence before the CYCCNT can be enabled. See for example the RESET_CYCLE_COUNTER in libbsp/arm/atsam/utils/utility.h. Note that this problem only occurs if no debugger is connected. A debugger most likely already enables the necessary module.
* score: Delete _CPU_Context_Fp_start()Sebastian Huber2017-01-261-3/+0
| | | | | | | | | | Since the FP area pointer is passed by reference in _CPU_Context_Initialize_fp() the optional FP area adjustment via _CPU_Context_Fp_start() is superfluous. It is also wrong with respect to memory management, e.g. pointer passed to _Workspace_Free() may be not the one returned by _Workspace_Allocate(). Close #1400.
* Adding ARM VFP V2 supportKevin Kirspel2017-01-241-0/+6
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* Remove CPU_BIG_ENDIAN and CPU_LITTLE_ENDIANSebastian Huber2017-01-241-10/+0
| | | | | | Use de-facto standard BYTE_ORDER instead. Close #2803.
* score: Fix ARM and PowerPC context initializationSebastian Huber2016-12-021-0/+1
| | | | Update #2751.
* arm: Fix _CPU_ISR_Is_enabled() for ARMv7-MSebastian Huber2016-11-241-1/+1
| | | | Update #2811.
* score: Robust thread dispatchSebastian Huber2016-11-231-0/+6
| | | | | | | | | | | | On SMP configurations, it is a fatal error to call blocking operating system with interrupts disabled, since this prevents delivery of inter-processor interrupts. This could lead to executing threads which are not allowed to execute resulting in undefined behaviour. The ARM Cortex-M port has a similar problem, since the interrupt state is not a part of the thread context. Update #2811.
* arm: Fix _ARMV4_Exception_interruptSebastian Huber2016-11-231-1/+1
| | | | | | | Use the right register to determine if a thread dispatch is allowed and necessary. Update #2751.
* arm: Fix Thumb-1 targetsSebastian Huber2016-11-212-10/+40
| | | | | | | We cannot use the MRS or MSR instructions in Thumb-1 mode. Stay in ARM mode for the Thumb-1 targets during interrupt low-level processing. Update #2751.
* arm: Fix ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLESebastian Huber2016-11-211-2/+4
| | | | Close #2816.
* score: Add _ISR_Is_enabled()Sebastian Huber2016-11-181-2/+9
| | | | | | | In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates a level parameter and returns a boolean value. Update #2811.
* arm: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-184-31/+94
| | | | Update #2751.
* arm: Simplify _ARMV4_Exception_interruptSebastian Huber2016-11-181-18/+22
| | | | | Move profiling code closer to bsp_interrupt_disable() to allow re-use of r9 later.
* arm: Use local labelsSebastian Huber2016-11-181-9/+9
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* score: Allow interrupts during thread dispatchSebastian Huber2016-11-181-3/+7
| | | | | | | | | Use a processor-specific interrupt frame during context switches in case the executing thread is longer executes on the processor and the heir thread is about to start execution. During this period we must not use a thread stack for interrupt processing. Update #2809.
* arm: Provide CPU_Interrupt_frame for ARMv4Sebastian Huber2016-11-182-3/+55
| | | | Update #2809.
* rtems: Conditionally define rtems_interrupt_frameSebastian Huber2016-11-181-1/+1
| | | | Update #2808.
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