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* arm: Fix ARMv7-M interrupt processingSebastian Huber2017-07-042-30/+48
| | | | | | | | | | | | Right after a "msr basepri_max, %[basepri]" instruction an interrupt service may still take place (observed at least on Cortex-M7). However, pendable service calls that are activated during this interrupt service may be delayed until interrupts are enable again. The _ARMV7M_Pendable_service_call() did not check that a thread dispatch is allowed. Move this test from _ARMV7M_Interrupt_service_leave() to _ARMV7M_Pendable_service_call(). Update #3060.
* Simplify TLS support in context switchSebastian Huber2017-06-091-11/+2
| | | | | | There is no need to save the thread pointer in _CPU_Context_switch() since it is a thread invariant. It is initialized once in _CPU_Context_Initialize().
* arm: Fix profiling support of Thumb-1 targetsSebastian Huber2017-05-231-1/+3
| | | | Update #2751.
* arm: Optimize context switchSebastian Huber2017-03-283-78/+55
| | | | | | | | | Set CPU_ENABLE_ROBUST_THREAD_DISPATCH to TRUE. In this case the interrupts are always enabled during a context switch even after interrupt processing (see #2751). Remove the CPSR from the context control since it contains only volatile bits. Close #2954.
* arm: Fix CPU context validation for Cortex-R4Sebastian Huber2017-03-092-7/+3
| | | | Do not touch the FPSCR[QC] bit since this is DNM/RAZ on Cortex-R4.
* arm: Remove legacy execption supportSebastian Huber2017-03-084-301/+0
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* bsps/arm: Fix Cortex-M DWT CPU counter.Christian Mauderer2017-01-301-1/+45
| | | | | | | | | It is necessary to enable the DWT using a special initialization sequence before the CYCCNT can be enabled. See for example the RESET_CYCLE_COUNTER in libbsp/arm/atsam/utils/utility.h. Note that this problem only occurs if no debugger is connected. A debugger most likely already enables the necessary module.
* score: Delete _CPU_Context_Fp_start()Sebastian Huber2017-01-261-3/+0
| | | | | | | | | | Since the FP area pointer is passed by reference in _CPU_Context_Initialize_fp() the optional FP area adjustment via _CPU_Context_Fp_start() is superfluous. It is also wrong with respect to memory management, e.g. pointer passed to _Workspace_Free() may be not the one returned by _Workspace_Allocate(). Close #1400.
* Adding ARM VFP V2 supportKevin Kirspel2017-01-241-0/+6
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* Remove CPU_BIG_ENDIAN and CPU_LITTLE_ENDIANSebastian Huber2017-01-241-10/+0
| | | | | | Use de-facto standard BYTE_ORDER instead. Close #2803.
* score: Fix ARM and PowerPC context initializationSebastian Huber2016-12-021-0/+1
| | | | Update #2751.
* arm: Fix _CPU_ISR_Is_enabled() for ARMv7-MSebastian Huber2016-11-241-1/+1
| | | | Update #2811.
* score: Robust thread dispatchSebastian Huber2016-11-231-0/+6
| | | | | | | | | | | | On SMP configurations, it is a fatal error to call blocking operating system with interrupts disabled, since this prevents delivery of inter-processor interrupts. This could lead to executing threads which are not allowed to execute resulting in undefined behaviour. The ARM Cortex-M port has a similar problem, since the interrupt state is not a part of the thread context. Update #2811.
* arm: Fix _ARMV4_Exception_interruptSebastian Huber2016-11-231-1/+1
| | | | | | | Use the right register to determine if a thread dispatch is allowed and necessary. Update #2751.
* arm: Fix Thumb-1 targetsSebastian Huber2016-11-212-10/+40
| | | | | | | We cannot use the MRS or MSR instructions in Thumb-1 mode. Stay in ARM mode for the Thumb-1 targets during interrupt low-level processing. Update #2751.
* arm: Fix ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLESebastian Huber2016-11-211-2/+4
| | | | Close #2816.
* score: Add _ISR_Is_enabled()Sebastian Huber2016-11-181-2/+9
| | | | | | | In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates a level parameter and returns a boolean value. Update #2811.
* arm: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-184-31/+94
| | | | Update #2751.
* arm: Simplify _ARMV4_Exception_interruptSebastian Huber2016-11-181-18/+22
| | | | | Move profiling code closer to bsp_interrupt_disable() to allow re-use of r9 later.
* arm: Use local labelsSebastian Huber2016-11-181-9/+9
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* score: Allow interrupts during thread dispatchSebastian Huber2016-11-181-3/+7
| | | | | | | | | Use a processor-specific interrupt frame during context switches in case the executing thread is longer executes on the processor and the heir thread is about to start execution. During this period we must not use a thread stack for interrupt processing. Update #2809.
* arm: Provide CPU_Interrupt_frame for ARMv4Sebastian Huber2016-11-182-3/+55
| | | | Update #2809.
* rtems: Conditionally define rtems_interrupt_frameSebastian Huber2016-11-181-1/+1
| | | | Update #2808.
* score: Move CPU_PER_CPU_CONTROL_SIZESebastian Huber2016-11-182-2/+4
| | | | | Move CPU_PER_CPU_CONTROL_SIZE and the optional CPU_Per_CPU_control to <rtems/score/cpuimpl.h> to hide it from <rtems.h>.
* score: Remove obsolete definesSebastian Huber2016-11-181-7/+0
| | | | The thread dispatch inline option is no longer used.
* arm: Use TPIDRPRW for current per-CPU controlSebastian Huber2016-11-184-9/+30
| | | | | | Use the previously unused TPIDRPRW register to get the per-CPU control of the current processor. This avoids instructions in GET_SELF_CPU_CONTROL which are not available in Thumb mode.
* score: Add <rtems/score/cpuimpl.h>Sebastian Huber2016-11-073-0/+35
| | | | | | The aim of this file is to encapsulate CPU port implementation details. This helps to hide implementation details from <rtems.h> which indirectly includes <rtems/score/cpu.h>.
* score/arm: Correct logic to select 64 byte cache line maximum size for Cortex-A.Pavel Pisa2016-10-041-2/+2
| | | | | | | | The use of actual cache line max bytes and minimum required alignment in architecture but not-BSP dependent code could be problematic because there exists even ARM instruction set implementations with 128 byte line length and real maximum can be quite problematic to say. But actually supported ARM BSPs should be OK with these values.
* score: Fix C/C++ compatibility issueSebastian Huber2016-09-231-4/+0
| | | | | | | Only use CPU_Per_CPU_control if it contains at least one filed. In GNU C empty structures have a size of zero. In C++ structures have a non-zero size. In case CPU_PER_CPU_CONTROL_SIZE is defined to zero, then this structure is not used anymore.
* arm: Add VFP context validate support for ARMv5Kevin Kirspel2016-08-192-5/+11
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* score: Fix printk() format specifiersSebastian Huber2016-07-261-2/+5
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* score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.Pavel Pisa2016-07-042-2/+9
| | | | | Some/many Cortex-A cores have data cache line length 64 bytes and maximum value has to be used for system structures alignment.
* arm/score and shared: define ARM hypervisor mode and alternate vector table ↵Pavel Pisa2016-07-041-0/+1
| | | | | | | | | base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example).
* score: Simplify priority bit map implementationSebastian Huber2016-06-081-2/+0
| | | | | | | | | | The priority bit map can deal with a maximum of 256 priority values ranging from 0 to 255. Consistently use an unsigned int for computation, due to the usual integer promotion rules. Make Priority_bit_map_Word definition architecture-independent and define it to uint16_t. This was already the case for all architectures except PowerPC. Adjust the PowerPC bitmap support accordingly.
* score: Delete CPU_USE_GENERIC_BITFIELD_DATASebastian Huber2016-06-081-2/+0
| | | | | | Rename __log2table into _Bitfield_Leading_zeros since it acually returns the count of leading zeros of an 8-bit integer. The value for zero is a bit odd. Provide it unconditionally.
* arm: Fix printk warnings.Chris Johns2016-06-031-16/+18
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* score: Rename _ISR_Disable() and _ISR_Enable()Sebastian Huber2016-05-201-2/+2
| | | | | | | | | Rename _ISR_Disable() into _ISR_Local_disable(). Rename _ISR_Enable() into _ISR_Local_enable(). Remove _Debug_Is_owner_of_giant(). This is a preparation to remove the Giant lock. Update #2555.
* score: Add CPU_MAXIMUM_PROCESSORSSebastian Huber2016-03-041-0/+2
| | | | Maximum number of processors of all systems supported by this CPU port.
* _ARMV7M_Is_vector_an_irq: Use ARMV7M_VECTOR_SYSTICK instead of hardcoded 16Martin Galvan2016-02-191-1/+2
| | | | Also add a comment explaining why we use that value.
* arm: Fix Cortex-M7 supportSebastian Huber2016-02-041-1/+2
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* score: Introduce CPU_CACHE_LINE_BYTESSebastian Huber2016-01-261-2/+4
| | | | | Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The actual processor may use no cache or a smaller cache line size.
* score: Delete obsolete CPU_TIMESTAMP_* definesSebastian Huber2016-01-251-2/+0
| | | | Update #2271.
* arm: Use DWT CYCCNT for timecounter if availableSebastian Huber2016-01-211-0/+27
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* arm: Honor cache for Cortex-M7 supportSebastian Huber2016-01-151-2/+11
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* arm: Accept Cortex-M7 multilibSebastian Huber2016-01-151-1/+1
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* Fix interrupt epilogue for ARMv7-AR and PowerPCSebastian Huber2015-11-121-0/+27
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* basedefs.h: Add and use RTEMS_NO_RETURNSebastian Huber2015-10-261-2/+2
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* SMP: Fix and optimize thread dispatchingSebastian Huber2015-09-281-15/+12
| | | | | | | | According to the C11 and C++11 memory models only a read-modify-write operation guarantees that we read the last value written in modification order. Avoid the sequential consistent thread fence and instead use the inter-processor interrupt to set the thread dispatch necessary indicator.
* ARMv7M: Improve exception handler routine and add comments on SP selectionMartin Galvan2015-09-231-11/+21
| | | | | | | | | This patch adds a brief description of how context state is saved into the SP on exception entry, and makes a few changes to _ARMV7M_Exception_default in order to make it a bit more efficient. I also removed the unused 'v7mfsz' input parameter. This should apply over Sudarshan's patch.
* Fix exception handler for supporting FPUSudarshan Rajagopalan2015-09-231-4/+4
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