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A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.
This has at least seven problems:
* The make preinstall step itself needs time and disk space.
* Errors in header files show up in the build tree copy. This makes it
hard for editors to open the right file to fix the error.
* There is no clear relationship between source and build tree header
files. This makes an audit of the build process difficult.
* The visibility of all header files in the build tree makes it
difficult to enforce API barriers. For example it is discouraged to
use BSP-specifics in the cpukit.
* An introduction of a new build system is difficult.
* Include paths specified by the -B option are system headers. This
may suppress warnings.
* The parallel build had sporadic failures on some hosts.
This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.
The new cpukit include directories are:
* cpukit/include
* cpukit/score/cpu/@RTEMS_CPU@/include
* cpukit/libnetworking
The new BSP include directories are:
* bsps/include
* bsps/@RTEMS_CPU@/include
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include
There are build tree include directories for generated files.
The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.
The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.
Update #3254.
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Set CPU_ENABLE_ROBUST_THREAD_DISPATCH to TRUE. In this case the
interrupts are always enabled during a context switch even after
interrupt processing (see #2751). Remove the CPSR from the context
control since it contains only volatile bits.
Close #2954.
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It is necessary to enable the DWT using a special initialization
sequence before the CYCCNT can be enabled. See for example the
RESET_CYCLE_COUNTER in libbsp/arm/atsam/utils/utility.h.
Note that this problem only occurs if no debugger is connected. A
debugger most likely already enables the necessary module.
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Since the FP area pointer is passed by reference in
_CPU_Context_Initialize_fp() the optional FP area adjustment via
_CPU_Context_Fp_start() is superfluous. It is also wrong with respect
to memory management, e.g. pointer passed to _Workspace_Free() may be
not the one returned by _Workspace_Allocate().
Close #1400.
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Use de-facto standard BYTE_ORDER instead.
Close #2803.
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Update #2811.
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On SMP configurations, it is a fatal error to call blocking operating
system with interrupts disabled, since this prevents delivery of
inter-processor interrupts. This could lead to executing threads which
are not allowed to execute resulting in undefined behaviour.
The ARM Cortex-M port has a similar problem, since the interrupt state
is not a part of the thread context.
Update #2811.
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We cannot use the MRS or MSR instructions in Thumb-1 mode. Stay in ARM
mode for the Thumb-1 targets during interrupt low-level processing.
Update #2751.
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Close #2816.
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In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates
a level parameter and returns a boolean value.
Update #2811.
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Update #2751.
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Update #2809.
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Update #2808.
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Move CPU_PER_CPU_CONTROL_SIZE and the optional CPU_Per_CPU_control to
<rtems/score/cpuimpl.h> to hide it from <rtems.h>.
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The thread dispatch inline option is no longer used.
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Use the previously unused TPIDRPRW register to get the per-CPU control
of the current processor. This avoids instructions in
GET_SELF_CPU_CONTROL which are not available in Thumb mode.
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The aim of this file is to encapsulate CPU port implementation details.
This helps to hide implementation details from <rtems.h> which
indirectly includes <rtems/score/cpu.h>.
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The use of actual cache line max bytes and minimum required alignment
in architecture but not-BSP dependent code could be problematic
because there exists even ARM instruction set implementations
with 128 byte line length and real maximum can be quite problematic
to say. But actually supported ARM BSPs should be OK with these values.
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Only use CPU_Per_CPU_control if it contains at least one filed. In GNU
C empty structures have a size of zero. In C++ structures have a
non-zero size. In case CPU_PER_CPU_CONTROL_SIZE is defined to zero,
then this structure is not used anymore.
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Some/many Cortex-A cores have data cache line length 64 bytes and maximum
value has to be used for system structures alignment.
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base access.
The main reason for inclusion of minimum hypervisor related defines
is that current ARM boards firmware and loaders (U-boot for example)
start loaded operating system kernel in HYP mode to allow it take
control of virtualization (Linux/KVM for example).
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The priority bit map can deal with a maximum of 256 priority values
ranging from 0 to 255. Consistently use an unsigned int for
computation, due to the usual integer promotion rules.
Make Priority_bit_map_Word definition architecture-independent and
define it to uint16_t. This was already the case for all architectures
except PowerPC. Adjust the PowerPC bitmap support accordingly.
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Rename __log2table into _Bitfield_Leading_zeros since it acually returns
the count of leading zeros of an 8-bit integer. The value for zero is a
bit odd. Provide it unconditionally.
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Maximum number of processors of all systems supported by this CPU port.
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Also add a comment explaining why we use that value.
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Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The
actual processor may use no cache or a smaller cache line size.
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Update #2271.
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The stack pointer must be aligned on 8 byte boundary on ARM, so the size of
the exception frame must be a multiple of 8 bytes. Otherwise we might/will
get an alignment fault, when executing code in the data abort handler for
example.
Close #2318.
Signed-off-by: Daniel Krueger <daniel.krueger@systec-electronic.com>
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Update #2268.
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ARMv6-M is not supported since we cannot directly use the ARMv7-M code
due to some inline assembler statements.
Close #2231.
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Converting 64-bit nanoseconds values into the common struct timeval or
struct timespec formats requires a 64-bit division to get the seconds
value. Performance analysis of high network loads revealed that this is
too costly on ARM.
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RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
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Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.
This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.
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This floating point unit is available in Cortex-M4 processors and
defined by ARMv7-M. This adds basic support for other VFP-D16 variants.
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Fix context switch on SMP for ARM, PowerPC and SPARC.
Atomically test and set the is executing indicator of the heir context
to ensure that at most one processor uses the heir context. Break the
busy wait loop also due to heir updates.
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We must not alter the is executing indicator in
_CPU_Context_Initialize() since this would cause an invalid state during
a self restart.
The is executing indicator must be valid at creation time since
otherwise _Thread_Kill_zombies() uses an undefined value for not started
threads. This could result in a system life lock.
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The current implementation of task migration in RTEMS has some
implications with respect to the interrupt latency. It is crucial to
preserve the system invariant that a task can execute on at most one
processor in the system at a time. This is accomplished with a boolean
indicator in the task context. The processor architecture specific
low-level task context switch code will mark that a task context is no
longer executing and waits that the heir context stopped execution
before it restores the heir context and resumes execution of the heir
task. So there is one point in time in which a processor is without a
task. This is essential to avoid cyclic dependencies in case multiple
tasks migrate at once. Otherwise some supervising entity is necessary to
prevent life-locks. Such a global supervisor would lead to scalability
problems so this approach is not used. Currently the thread dispatch is
performed with interrupts disabled. So in case the heir task is
currently executing on another processor then this prolongs the time of
disabled interrupts since one processor has to wait for another
processor to make progress.
It is difficult to avoid this issue with the interrupt latency since
interrupts normally store the context of the interrupted task on its
stack. In case a task is marked as not executing we must not use its
task stack to store such an interrupt context. We cannot use the heir
stack before it stopped execution on another processor. So if we enable
interrupts during this transition we have to provide an alternative task
independent stack for this time frame. This issue needs further
investigation.
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Add and use _CPU_SMP_Start_processor(). Add and use
_CPU_SMP_Finalize_initialization(). This makes most
_CPU_SMP_Initialize() functions a bit simpler since we can calculate the
minimum value of the count of processors requested by the application
configuration and the count of physically or virtually available
processors in the high-level code.
The CPU port has now the ability to signal a processor start failure.
With the support for clustered/partitioned scheduling the presence of
particular processors can be configured to be optional or mandatory.
There will be a fatal error only in case mandatory processors are not
present.
The CPU port may use a timeout to monitor the start of a processor.
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