| Commit message (Collapse) | Author | Age | Files | Lines |
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In _ARMV4_Exception_fiq_default, set the F bit of the SPSR so that when
it gets loaded back to the CPSR in save_more_context it won't re-enable
the FIQs.
Tested on a TMS570LS3137.
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This floating point unit is available in Cortex-M4 processors and
defined by ARMv7-M. This adds basic support for other VFP-D16 variants.
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Use the right stack pointer value for the exception frame. Assume that
we do not have a double abort exception.
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Add and use _ARMV4_Exception_undef_default(),
_ARMV4_Exception_swi_default(), _ARMV4_Exception_data_abort_default(),
_ARMV4_Exception_pref_abort_default(),
_ARMV4_Exception_reserved_default(), _ARMV4_Exception_irq_default(), and
_ARMV4_Exception_fiq_default().
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