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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-05-08 09:30:31 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-05-10 12:10:14 +0200 |
| commit | cfd8d7a3d73a10ae7cdbbfe5eb39839c46a5c77e (patch) | |
| tree | 5b694eb680b61129908a274b218d5f67fa0d34d6 /cpukit/score/cpu/arm/armv4-exception-default.S | |
| parent | arm: Simplify architecture selection (diff) | |
| download | rtems-cfd8d7a3d73a10ae7cdbbfe5eb39839c46a5c77e.tar.bz2 | |
arm: Support VFP-D32 and Neon
Diffstat (limited to 'cpukit/score/cpu/arm/armv4-exception-default.S')
| -rw-r--r-- | cpukit/score/cpu/arm/armv4-exception-default.S | 47 |
1 files changed, 36 insertions, 11 deletions
diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S b/cpukit/score/cpu/arm/armv4-exception-default.S index e5520d5817..a5fe415fb4 100644 --- a/cpukit/score/cpu/arm/armv4-exception-default.S +++ b/cpukit/score/cpu/arm/armv4-exception-default.S @@ -21,6 +21,9 @@ #ifdef ARM_MULTILIB_ARCH_V4 +#define MORE_CONTEXT_SIZE \ + (ARM_EXCEPTION_FRAME_SIZE - ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET) + .extern _ARM_Exception_default .globl _ARMV4_Exception_undef_default @@ -38,7 +41,7 @@ _ARMV4_Exception_undef_default: /* Save context and load vector */ - sub sp, #20 + sub sp, #MORE_CONTEXT_SIZE stmdb sp!, {r0-r12} mov r4, #1 @@ -47,7 +50,7 @@ _ARMV4_Exception_undef_default: _ARMV4_Exception_swi_default: /* Save context and load vector */ - sub sp, #20 + sub sp, #MORE_CONTEXT_SIZE stmdb sp!, {r0-r12} mov r4, #2 @@ -56,7 +59,7 @@ _ARMV4_Exception_swi_default: _ARMV4_Exception_pref_abort_default: /* Save context and load vector */ - sub sp, #20 + sub sp, #MORE_CONTEXT_SIZE stmdb sp!, {r0-r12} mov r4, #3 @@ -65,28 +68,28 @@ _ARMV4_Exception_pref_abort_default: _ARMV4_Exception_data_abort_default: /* Save context and load vector */ - sub sp, #20 + sub sp, #MORE_CONTEXT_SIZE stmdb sp!, {r0-r12} mov r4, #4 _ARMV4_Exception_reserved_default: /* Save context and load vector */ - sub sp, #20 + sub sp, #MORE_CONTEXT_SIZE stmdb sp!, {r0-r12} mov r4, #5 _ARMV4_Exception_irq_default: /* Save context and load vector */ - sub sp, #20 + sub sp, #MORE_CONTEXT_SIZE stmdb sp!, {r0-r12} mov r4, #6 _ARMV4_Exception_fiq_default: /* Save context and load vector */ - sub sp, #20 + sub sp, #MORE_CONTEXT_SIZE stmdb sp!, {r0-r12} mov r4, #7 @@ -99,14 +102,36 @@ save_more_context: orr r5, r3, #ARM_PSR_I bic r5, #ARM_PSR_T msr cpsr, r5 - mov r0, sp + sub r0, sp, #ARM_EXCEPTION_FRAME_SIZE mov r1, lr msr cpsr, r7 - add r5, sp, #72 - stmdb r5!, {r0-r4} + mov r5, #0 + add r6, sp, #ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET + stm r6, {r0-r5} - /* Call high level handler */ + /* Argument for high level handler */ mov r0, sp + +#ifdef ARM_MULTILIB_VFP_D32 + /* Ensure that the FPU is enabled */ + vmrs r1, FPEXC + tst r1, #(1 << 30) + beq fpu_save_done + + add r3, sp, #ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET + sub sp, #(ARM_VFP_CONTEXT_SIZE + 4) + add r4, sp, #4 + bic r4, r4, #7 + str r4, [r3] + vmrs r2, FPSCR + stmia r4!, {r1-r2} + vstmia r4!, {d0-d15} + vstmia r4!, {d16-d31} + +fpu_save_done: +#endif + + /* Call high level handler */ SWITCH_FROM_ARM_TO_THUMB r1 bl _ARM_Exception_default |