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* GRETH: Interrupt Handler Uses Wrong EventsChristian Spindeldreier2017-01-121-1/+1
| | | | closes #2796.
* Remove texinfo format documentation. Replaced by Sphinx formatted documentation.Joel Sherrill2017-01-111-2/+2
| | | | closes #2812.
* Rename *.s to *.SSebastian Huber2016-12-202-1/+1
| | | | | | Consistently use *.S for assembler files. Close #2701.
* bsp/atsam: Use standard XDMA throughoutSebastian Huber2016-12-208-32/+6
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* bsp/atsam: Use standard XDMA for QSPI supportSebastian Huber2016-12-161-9/+1
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* bsp/atsam: Add SC16IS752 supportSebastian Huber2016-12-164-0/+158
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* bsp/atsam: Move interrupt setup to PIO_Configure()Sebastian Huber2016-12-162-25/+21
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* bsp/atsam: System initialization for PIO IRQsSebastian Huber2016-12-163-124/+127
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* bsp/atsamv: Move XDMAD instance out of SPI driverSebastian Huber2016-12-163-89/+44
| | | | Use system initialization for XDMAD. Remove support for polling.
* bsp/atsam: Move XDMA IRQ handler to XDMA moduleSebastian Huber2016-12-154-242/+203
| | | | | The XDMA is shared by all DMA capable modules. Placing the XDMA interrupt handler into the SPI module is wrong.
* bsp/atsam: Use _Assert() instead of assert()Sebastian Huber2016-12-151-66/+66
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* bsp/atsam: Use inline functions for XDMA accessSebastian Huber2016-12-153-609/+508
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* bsp/atsam: Optimize SPI interruptSebastian Huber2016-12-141-40/+36
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* bsp/atsam: Simplify SPI transfer statusSebastian Huber2016-12-141-7/+9
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* bsp/atsam: Reduce context switches for SPI transfSebastian Huber2016-12-141-99/+107
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* bsp/atsam: Optimize SPI DMA transfer setupSebastian Huber2016-12-141-73/+48
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* bsp/atsam: Simplify SPI DMA transfer setupSebastian Huber2016-12-141-70/+38
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* bsp/atsam: Simplify SPI DMA initializationSebastian Huber2016-12-141-56/+23
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* bsp/atsam: Simplify SPI interrupt handlerSebastian Huber2016-12-141-7/+1
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* bsp/atsam: Remove superfluous irq fieldSebastian Huber2016-12-141-8/+6
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* bsp/atsam: Remove duplicate SPI register fieldSebastian Huber2016-12-141-4/+3
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* bsp/atsam: Simplify SPI initializationSebastian Huber2016-12-143-36/+23
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* bsp/atsam: Hide details of SPI driverSebastian Huber2016-12-142-31/+24
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* bsp/atsam: Align SPI API with PIO_Configure()Sebastian Huber2016-12-143-27/+44
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* bsp/atsam: Avoid to power on/off the SPI moduleSebastian Huber2016-12-142-22/+9
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* bsp/atsam: Speed up SPI DMA transfer startSebastian Huber2016-12-142-9/+10
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* bsp/atsam: Optimize transfer setup checksSebastian Huber2016-12-141-34/+32
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* bsp/atsam: No timeout for SPI DMA transfersSebastian Huber2016-12-141-7/+3
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* libdl: Add C++ exception support to loaded modules.Chris Johns2016-12-141-4/+0
| | | | | | This has been tested on SPARC, i386, PowerPC and ARM. Closes #2767.
* Rename is_internal to always_set_to_falseSebastian Huber2016-12-1217-17/+17
| | | | Update #2825.
* score: Remove fatal is internal indicatorSebastian Huber2016-12-091-2/+0
| | | | | | | | | The fatal is internal indicator is redundant since the fatal source and error code uniquely identify a fatal error. Keep the fatal user extension is internal parameter for backward compatibility and set it to false always. Update #2825.
* testsuite: Add test states to the testsuit configuration files.Chris Johns2016-12-0756-510/+514
| | | | | | | | | | | | | | | | Change the testsuite configuration files to hold state information about a test. The states are: exclude - Do not build the test expected-fail - The test is expected to fail indeterminate - The test may pass or may fail A message is printed just after the test's BEGIN message to indicate there is a special state for the test. No state message means the test is expected to pass. This support requires tests are correctly written to the use standard support to begin and end a test.
* score: Fix ARM and PowerPC context initializationSebastian Huber2016-12-021-0/+1
| | | | Update #2751.
* libdebugger: Build for ARM's without a CP15.Chris Johns2016-12-026-1/+25
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* Remove sparc/sis BSP.Joel Sherrill2016-11-299-104/+0
| | | | closes #2810.
* arm/zynq: Wait for the UART TX FIFO to empty on reset.Chris Johns2016-11-293-0/+24
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* sparc: Optimize _ISR_Handler()Sebastian Huber2016-11-286-81/+107
| | | | | | Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the PSR[EF] state of the interrupted context via new system call syscall_irqdis_fp in case floating-point support is enabled.
* or1k: Avoid multiple iterations over cacheMartin Erik Werner2016-11-281-0/+27
| | | | | | | | | Previously, if the cache range operations were called with a range that was larger than the cache size, this would lead to multiple iterations over the cache, which is unnecessary. Limit this so that if the range is larger than the cache size, the operations will only iterate over the whole cache once.
* or1k: Remove secondary functions in cache managerMartin Erik Werner2016-11-281-56/+34
| | | | | | | | | | Move the code of the _CPU_OR1K_Cache_{enable,disable}_* functions into the equivalent exported _CPU_cache_{enable,disable}_* functions instead, and then delete them, in order to reduce the code indirection and aid readability. This does not touch the currently unused prefetch, writeback, and lock functions.
* or1k: Avoid excessive ISR toggle in cache managerMartin Erik Werner2016-11-282-44/+123
| | | | | | | | | | | | | | | | | Previously _ISR_Local_{disable,enable}() was executed twice for each cache line operation, and since operations over the entire cache were implemented by calling the single-line operations in a loop, this made those operations rather costly. Fix the double-toggle by calling _OR1K_mtspr() directly, and removing the now-unused corresponding _CPU_OR1K_Cache_* functions. Fix the entire-operations by moving the ISR toggle outside of the loop, and by calling _OR1K_mtspr() directly instead of the single-line operations. Also implement range functions, since otherwise the cache manager falls back on looping over the single-line operations.
* or1k: Indent & comment fix in cache.cMartin Erik Werner2016-11-281-14/+25
| | | | | | | * Fix indentation of variable declarations. * Change commented-out asm -> __asm__ to meet c99 standard if uncommented.
* or1k: Add functions for entire cache operationsMartin Erik Werner2016-11-281-3/+42
| | | | | | | | | | | | | | | Add functions for flushing and invalidating whole cache. Since we don't have system calls that can operate on anything more than a single cache line, these simply retrieves the cache size and iterates over the full size, invalidating each line. The current implementation assumes that there's only one level of cache. These changes were contributed by Antmicro under contract by ÅAC Microtec AB. Close #2602
* bsps/arm: Add Cortex-M DWT CPU counterSebastian Huber2016-11-243-1/+57
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* score: Fix interrupt profilingSebastian Huber2016-11-241-20/+13
| | | | | | | | | | Callers of _Thread_Do_dispatch() must have a valid Per_CPU_Control::Stats::thread_dispatch_disabled_instant. Call _Profiling_Outer_most_interrupt_entry_and_exit() with the interrupt stack to not exceed Per_CPU_Control::Interrupt_frame. Update #2751.
* powerpc: Fix interrupt profiling for e6500Sebastian Huber2016-11-241-1/+3
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* bsp/lpc23xx_tli800: Disable tar01 testSebastian Huber2016-11-231-0/+1
| | | | Close #2824.
* powerpc/mpc5xx: Rename CPU_Interrupt_frameSebastian Huber2016-11-212-4/+4
| | | | | | The MPC5XX support uses a legacy interrupt/exception infrastructure. Close #2819.
* powerpc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-182-20/+66
| | | | Update #2751.
* sparc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-181-5/+5
| | | | Update #2751.
* score: Allow interrupts during thread dispatchSebastian Huber2016-11-182-19/+29
| | | | | | | | | Use a processor-specific interrupt frame during context switches in case the executing thread is longer executes on the processor and the heir thread is about to start execution. During this period we must not use a thread stack for interrupt processing. Update #2809.
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