| Commit message (Collapse) | Author | Age | Files | Lines |
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Consistently use *.S for assembler files.
Close #2701.
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Use system initialization for XDMAD. Remove support for polling.
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The XDMA is shared by all DMA capable modules. Placing the XDMA
interrupt handler into the SPI module is wrong.
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This has been tested on SPARC, i386, PowerPC and ARM.
Closes #2767.
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Update #2825.
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The fatal is internal indicator is redundant since the fatal source and
error code uniquely identify a fatal error. Keep the fatal user
extension is internal parameter for backward compatibility and set it to
false always.
Update #2825.
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Change the testsuite configuration files to hold state information about
a test. The states are:
exclude - Do not build the test
expected-fail - The test is expected to fail
indeterminate - The test may pass or may fail
A message is printed just after the test's BEGIN message to indicate
there is a special state for the test. No state message means the test
is expected to pass.
This support requires tests are correctly written to the use standard
support to begin and end a test.
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Update #2751.
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closes #2810.
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Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the
PSR[EF] state of the interrupted context via new system call
syscall_irqdis_fp in case floating-point support is enabled.
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Previously, if the cache range operations were called with a range that
was larger than the cache size, this would lead to multiple iterations
over the cache, which is unnecessary.
Limit this so that if the range is larger than the cache size, the
operations will only iterate over the whole cache once.
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Move the code of the _CPU_OR1K_Cache_{enable,disable}_* functions into the
equivalent exported _CPU_cache_{enable,disable}_* functions instead, and
then delete them, in order to reduce the code indirection and aid
readability.
This does not touch the currently unused prefetch, writeback, and lock
functions.
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Previously _ISR_Local_{disable,enable}() was executed twice for each
cache line operation, and since operations over the entire cache were
implemented by calling the single-line operations in a loop, this made
those operations rather costly.
Fix the double-toggle by calling _OR1K_mtspr() directly, and removing
the now-unused corresponding _CPU_OR1K_Cache_* functions.
Fix the entire-operations by moving the ISR toggle outside of the
loop, and by calling _OR1K_mtspr() directly instead of the single-line
operations.
Also implement range functions, since otherwise the cache manager falls
back on looping over the single-line operations.
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* Fix indentation of variable declarations.
* Change commented-out asm -> __asm__ to meet c99 standard if
uncommented.
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Add functions for flushing and invalidating whole cache.
Since we don't have system calls that can operate on anything more than
a single cache line, these simply retrieves the cache size and iterates
over the full size, invalidating each line.
The current implementation assumes that there's only one level of cache.
These changes were contributed by Antmicro under contract by ÅAC
Microtec AB.
Close #2602
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Callers of _Thread_Do_dispatch() must have a valid
Per_CPU_Control::Stats::thread_dispatch_disabled_instant.
Call _Profiling_Outer_most_interrupt_entry_and_exit() with the interrupt
stack to not exceed Per_CPU_Control::Interrupt_frame.
Update #2751.
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Close #2824.
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The MPC5XX support uses a legacy interrupt/exception infrastructure.
Close #2819.
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Update #2751.
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Update #2751.
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Use a processor-specific interrupt frame during context switches in case
the executing thread is longer executes on the processor and the heir
thread is about to start execution. During this period we must not use
a thread stack for interrupt processing.
Update #2809.
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Rename ppc_exc_min_frame to CPU_Interrupt_frame. Move it and the
corresponding defines to <rtems/score/cpuimpl.h>.
Update #2809.
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The only remaining user of CPU_Interrupt_frame on PowerPC is the mpc5xx
support. Move it to here.
Update #2809.
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