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* powerpc/new-exceptions/bspsupport/ppc_exc_print.c: Fix printf() format warningsJoel Sherrill2017-04-241-2/+2
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* powerpc/mpc5xx/console-generic/console-generic.c: Use updated struct termios ↵Joel Sherrill2017-04-241-2/+2
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* libcpu/../mpc5xx/.../vectors_init.c: Using inttype macros fixes 39 format ↵Cillian O'Donnell2017-04-071-39/+41
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* bsps/arm: Add Performance Monitors ExtensionSebastian Huber2017-03-271-1/+446
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* termios: Synchronize with latest FreeBSD headersKevin Kirspel2017-03-2214-33/+38
| | | | | | | | | | | Adding modified FreeBSD headers to synchronize RTEMS termios with FreeBSD. Modify termios to support dedicated input and output baud for termios structure. Updated BSPs to use dedicated input and output baud in termios structure. Updated tools to use dedicated input and output baud in termios structure. Updated termios testsuites to use dedicated input and output baud in termios structure. Close #2897.
* powerpc: Optimize AltiVec context switchSebastian Huber2017-03-072-31/+30
| | | | | | Use r8 instead of r5 to slightly optimize _CPU_Context_switch(). It is not a big deal, however, we already assume r12 is used by _CPU_Context_switch(). Treat r5 the in same way.
* powerpc: Fix AltiVec context switchSebastian Huber2017-03-071-12/+12
| | | | Update #2751.
* powerpc: Fix warningsSebastian Huber2017-03-021-1/+1
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* powerpc: Fix interrupt thread dispatchSebastian Huber2017-03-021-2/+1
| | | | Update #2751.
* bsps/powerpc: Fix warningSebastian Huber2017-02-151-2/+0
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* bsps/arm: Fix prototypeSebastian Huber2017-02-151-1/+1
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* bsps/powerpc: Fix warningsSebastian Huber2017-02-154-58/+61
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* score: Fix ARM and PowerPC context initializationSebastian Huber2016-12-021-0/+1
| | | | Update #2751.
* libdebugger: Build for ARM's without a CP15.Chris Johns2016-12-021-1/+2
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* sparc: Optimize _ISR_Handler()Sebastian Huber2016-11-281-0/+37
| | | | | | Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the PSR[EF] state of the interrupted context via new system call syscall_irqdis_fp in case floating-point support is enabled.
* or1k: Avoid multiple iterations over cacheMartin Erik Werner2016-11-281-0/+27
| | | | | | | | | Previously, if the cache range operations were called with a range that was larger than the cache size, this would lead to multiple iterations over the cache, which is unnecessary. Limit this so that if the range is larger than the cache size, the operations will only iterate over the whole cache once.
* or1k: Remove secondary functions in cache managerMartin Erik Werner2016-11-281-56/+34
| | | | | | | | | | Move the code of the _CPU_OR1K_Cache_{enable,disable}_* functions into the equivalent exported _CPU_cache_{enable,disable}_* functions instead, and then delete them, in order to reduce the code indirection and aid readability. This does not touch the currently unused prefetch, writeback, and lock functions.
* or1k: Avoid excessive ISR toggle in cache managerMartin Erik Werner2016-11-282-44/+123
| | | | | | | | | | | | | | | | | Previously _ISR_Local_{disable,enable}() was executed twice for each cache line operation, and since operations over the entire cache were implemented by calling the single-line operations in a loop, this made those operations rather costly. Fix the double-toggle by calling _OR1K_mtspr() directly, and removing the now-unused corresponding _CPU_OR1K_Cache_* functions. Fix the entire-operations by moving the ISR toggle outside of the loop, and by calling _OR1K_mtspr() directly instead of the single-line operations. Also implement range functions, since otherwise the cache manager falls back on looping over the single-line operations.
* or1k: Indent & comment fix in cache.cMartin Erik Werner2016-11-281-14/+25
| | | | | | | * Fix indentation of variable declarations. * Change commented-out asm -> __asm__ to meet c99 standard if uncommented.
* or1k: Add functions for entire cache operationsMartin Erik Werner2016-11-281-3/+42
| | | | | | | | | | | | | | | Add functions for flushing and invalidating whole cache. Since we don't have system calls that can operate on anything more than a single cache line, these simply retrieves the cache size and iterates over the full size, invalidating each line. The current implementation assumes that there's only one level of cache. These changes were contributed by Antmicro under contract by ÅAC Microtec AB. Close #2602
* score: Fix interrupt profilingSebastian Huber2016-11-241-20/+13
| | | | | | | | | | Callers of _Thread_Do_dispatch() must have a valid Per_CPU_Control::Stats::thread_dispatch_disabled_instant. Call _Profiling_Outer_most_interrupt_entry_and_exit() with the interrupt stack to not exceed Per_CPU_Control::Interrupt_frame. Update #2751.
* powerpc: Fix interrupt profiling for e6500Sebastian Huber2016-11-241-1/+3
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* powerpc/mpc5xx: Rename CPU_Interrupt_frameSebastian Huber2016-11-212-4/+4
| | | | | | The MPC5XX support uses a legacy interrupt/exception infrastructure. Close #2819.
* powerpc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-182-20/+66
| | | | Update #2751.
* score: Allow interrupts during thread dispatchSebastian Huber2016-11-181-12/+17
| | | | | | | | | Use a processor-specific interrupt frame during context switches in case the executing thread is longer executes on the processor and the heir thread is about to start execution. During this period we must not use a thread stack for interrupt processing. Update #2809.
* powerpc: Add up to date CPU_Interrupt_frameSebastian Huber2016-11-183-379/+4
| | | | | | | Rename ppc_exc_min_frame to CPU_Interrupt_frame. Move it and the corresponding defines to <rtems/score/cpuimpl.h>. Update #2809.
* powerpc: Move legacy CPU_Interrupt_frameSebastian Huber2016-11-181-0/+33
| | | | | | | The only remaining user of CPU_Interrupt_frame on PowerPC is the mpc5xx support. Move it to here. Update #2809.
* bsps/powerpc: Avoid use of CPU_Interrupt_frameSebastian Huber2016-11-181-3/+3
| | | | | | | This type is not relevant for the code since only a pointer is passed around. Update #2809.
* sparc64: Rename CPU_Minimum_stack_frameSebastian Huber2016-11-181-1/+1
| | | | | | | | Rename SPARC64-specific CPU_Minimum_stack_frame to SPARC64_Minimum_stack_frame. Rename SPARC64-specific CPU_MINIMUM_STACK_FRAME_SIZE to SPARC64_MINIMUM_STACK_FRAME_SIZE. Update #2809.
* bsps/mips: Use <libcpu/isr_entries.h>Sebastian Huber2016-11-181-0/+2
| | | | Avoid duplicate mips_vector_isr_handlers() declarations.
* powerpc: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2016-11-101-1/+8
| | | | | | | | Add _CPU_Get_current_per_CPU_control() on SMP configurations. Use SPRG0 for the current per-CPU control. This reduces the code size by three instructions and is slightly faster. Update #2805.
* score: Add and use Thread_Control::is_idleSebastian Huber2016-11-092-10/+2
| | | | Update #2797.
* powerpc: Fix SMP context switchSebastian Huber2016-09-081-61/+62
| | | | | | We need the unmodified r4 for get_potential_new_heir. This partially reverts commit 8d785f72d9610fb80a65d7848404f0f7507e026c.
* bsps/arm: reorganize CP15 code to allow clean and invalidate ARMv7 cache by ↵Pavel Pisa2016-09-071-48/+60
| | | | | | | level. New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level can be used to maintain single cache level (instruction or data).
* bsps/arm: use defines for cache type register format field.Pavel Pisa2016-09-071-9/+30
| | | | | | The change documents meaning of codes and opens well defined way to use cache type format for cache examination/debugging outside of arm-cp15.h file.
* arm/bsps: CP15 and basic cache support entire cache clean for more ↵Pavel Pisa2016-07-201-2/+42
| | | | | | | | | | | | | | | | | architecture variants now. Next cache operations should work on most of cores now rtems_cache_flush_entire_data() rtems_cache_invalidate_entire_data() rtems_cache_invalidate_entire_instruction() Instruction cache invalidate works on the first level for now only. Data cacache operations are extended to ensure flush/invalidate on all cache levels. The CP15 arm_cp15_data_cache_clean_all_levels() function extended to continue through unified levels too (ctype = 4).
* bsps/arm: do not disable MMU during translation table management operations.Pavel Pisa2016-07-201-0/+16
| | | | | | | | | | | | | | | | | | | | Disabling MMU requires complex cache flushing and invalidation operations. There is almost no way how to do that right on SMP system without stopping all other CPUs. On the other hand, there is documented sequence of operations which should be used according to ARM manual and it guarantees even distribution of maintenance operations to other cores for last generation of Cortex-A cores with multiprocessor extension. This change could require addition of appropriate entry to arm_cp15_start_mmu_config_table for some BSPs to ensure that MMU table stays accessible after MMU is enabled { .begin = (uint32_t) bsp_translation_table_base, .end = (uint32_t) bsp_translation_table_base + 0x4000, .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED }
* bsps/powerpc: Fix AtliVec context switchSebastian Huber2016-07-192-62/+68
| | | | | | | Properly pass the stack aligned context to _CPU_Context_switch_altivec() since _CPU_altivec_ctxt_off defined via ppc_context. Close #2761.
* Beaglebone: Update PWM driver imported from BBBIOPunit Vara2016-07-041-1/+96
| | | | | | This patch adapts the previously added Beaglebone PWM code from BBBIO to RTEMS. This work was done in the context of the Google Summer of Code 2016, and further patches will follow to improve the code quality and documentation.
* bsps/arm: basic on core cache support changed to use l1 functions.Pavel Pisa2016-07-041-3/+28
| | | | | | | | | | | | | | The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem.
* bsps/arm: Change code to explicit selection of cache implementation for ARM ↵Pavel Pisa2016-07-041-104/+30
| | | | | | | | | | | | | | | | | | | | | | | BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support
* rtems+bsps/cache: Define cache manager operations for code synchronization ↵Pavel Pisa2016-07-041-0/+42
| | | | | | | | | | | | | | and maximal alignment. There is need for unambiguous named and defined cache function which should be called when code is updated, loaded or is self-modifying. There should be function to obtain maximal cache line length as well. This function can and should be used for allocations which can be used for data and or code and ensures that there are no partial cache lines overlaps on start and end of allocated region.
* arm/score and shared: define ARM hypervisor mode and alternate vector table ↵Pavel Pisa2016-07-041-0/+30
| | | | | | | | | base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example).
* score: Rename _ISR_Disable() and _ISR_Enable()Sebastian Huber2016-05-207-54/+54
| | | | | | | | | Rename _ISR_Disable() into _ISR_Local_disable(). Rename _ISR_Enable() into _ISR_Local_enable(). Remove _Debug_Is_owner_of_giant(). This is a preparation to remove the Giant lock. Update #2555.
* score: Rename _ISR_Disable_without_giant()Sebastian Huber2016-05-201-12/+12
| | | | | | | | | Rename _ISR_Disable_without_giant() into _ISR_Local_disable(). Rename _ISR_Enable_without_giant() into _ISR_Local_enable(). This is a preparation to remove the Giant lock. Update #2555.
* score: _Thread_Dispatch_increment_disable_level()Sebastian Huber2016-05-204-8/+8
| | | | | | | | | | Avoid _Thread_Dispatch_increment_disable_level() and _Thread_Dispatch_decrement_disable_level() and thus the Giant lock. This is a preparation to remove the Giant lock. Update #2555.
* bsps/arm: CP15 support for flush prefetch buffer and table base control.Pavel Pisa2016-05-191-0/+48
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* libcpu/m68k/mcf5272/clock/ckinit.c: Fix warning by including <rtems/clockdrv.h>Joel Sherrill2016-03-271-0/+1
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* libcpu/m68k/mcf5206/clock/ckinit.c: Fix warning by including <rtems/clockdrv.h>Joel Sherrill2016-03-271-0/+1
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* libcpu/bfin/clock/clock.c: Fix warning by including <rtems/clockdrv.h>Joel Sherrill2016-03-271-0/+2
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