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* Beaglebone: Update PWM driver imported from BBBIOPunit Vara2016-07-041-1/+96
| | | | | | This patch adapts the previously added Beaglebone PWM code from BBBIO to RTEMS. This work was done in the context of the Google Summer of Code 2016, and further patches will follow to improve the code quality and documentation.
* bsps/arm: basic on core cache support changed to use l1 functions.Pavel Pisa2016-07-041-3/+28
| | | | | | | | | | | | | | The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem.
* bsps/arm: Change code to explicit selection of cache implementation for ARM ↵Pavel Pisa2016-07-041-104/+30
| | | | | | | | | | | | | | | | | | | | | | | BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support
* rtems+bsps/cache: Define cache manager operations for code synchronization ↵Pavel Pisa2016-07-041-0/+42
| | | | | | | | | | | | | | and maximal alignment. There is need for unambiguous named and defined cache function which should be called when code is updated, loaded or is self-modifying. There should be function to obtain maximal cache line length as well. This function can and should be used for allocations which can be used for data and or code and ensures that there are no partial cache lines overlaps on start and end of allocated region.
* arm/score and shared: define ARM hypervisor mode and alternate vector table ↵Pavel Pisa2016-07-041-0/+30
| | | | | | | | | base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example).
* score: Rename _ISR_Disable() and _ISR_Enable()Sebastian Huber2016-05-207-54/+54
| | | | | | | | | Rename _ISR_Disable() into _ISR_Local_disable(). Rename _ISR_Enable() into _ISR_Local_enable(). Remove _Debug_Is_owner_of_giant(). This is a preparation to remove the Giant lock. Update #2555.
* score: Rename _ISR_Disable_without_giant()Sebastian Huber2016-05-201-12/+12
| | | | | | | | | Rename _ISR_Disable_without_giant() into _ISR_Local_disable(). Rename _ISR_Enable_without_giant() into _ISR_Local_enable(). This is a preparation to remove the Giant lock. Update #2555.
* score: _Thread_Dispatch_increment_disable_level()Sebastian Huber2016-05-204-8/+8
| | | | | | | | | | Avoid _Thread_Dispatch_increment_disable_level() and _Thread_Dispatch_decrement_disable_level() and thus the Giant lock. This is a preparation to remove the Giant lock. Update #2555.
* bsps/arm: CP15 support for flush prefetch buffer and table base control.Pavel Pisa2016-05-191-0/+48
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* libcpu/m68k/mcf5272/clock/ckinit.c: Fix warning by including <rtems/clockdrv.h>Joel Sherrill2016-03-271-0/+1
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* libcpu/m68k/mcf5206/clock/ckinit.c: Fix warning by including <rtems/clockdrv.h>Joel Sherrill2016-03-271-0/+1
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* libcpu/bfin/clock/clock.c: Fix warning by including <rtems/clockdrv.h>Joel Sherrill2016-03-271-0/+2
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* sparc: Fix window underflow trap handlerDaniel Hellstrom2016-03-171-6/+6
| | | | | | | | | | | | The window underflow trap handler used %i5 which destroyed the %o5 of the calling context. Bug introduced by 0d3b5d47429effb350448d9e9123a67db722109f. Go back to the pre 0d3b5d47429effb350448d9e9123a67db722109f behaviour and use the two unused instructions in the trap vector to optimize a bit. Update #2651.
* i386: refactor libcpu/cpu.h into rtems/score/i386.hJoel Sherrill2016-03-037-484/+49
| | | | Fixes #2515.
* am335x irq handling improvementMartin Galvan2016-02-281-1/+2
| | | | | | | | | | | | | This patch makes the following changes to the Beaglebone IRQ handling code: - Disable support for nested interrupts. - Detect spurious IRQs using the SPURIOUSIRQ field of the INTC_SIR_IRQ register. - Acknowledge spurious IRQs by setting the NewIRQAgr bit of the INTC_CONTROL register. This cleans the SPURIOUSIRQ field and allows new interrupts to be generated. - Improve the get_mir_reg function a bit. Closes #2580.
* Delete unused API extensionsSebastian Huber2016-02-033-3/+0
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* score: Introduce CPU_CACHE_LINE_BYTESSebastian Huber2016-01-261-0/+8
| | | | | Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The actual processor may use no cache or a smaller cache line size.
* score: Fix simple timecounter supportSebastian Huber2016-01-191-14/+18
| | | | Update #2502.
* score: Introduce Thread_Entry_informationSebastian Huber2016-01-112-4/+4
| | | | | | | This avoids potential dead code in _Thread_Handler(). It gets rid of the dangerous function pointer casts. Update #2514.
* Fix interrupt epilogue for ARMv7-AR and PowerPCSebastian Huber2015-11-121-13/+38
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* basdefs.h: Add and use RTEMS_PACKEDSebastian Huber2015-10-261-1/+1
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* SMP: Fix and optimize thread dispatchingSebastian Huber2015-09-282-15/+19
| | | | | | | | According to the C11 and C++11 memory models only a read-modify-write operation guarantees that we read the last value written in modification order. Avoid the sequential consistent thread fence and instead use the inter-processor interrupt to set the thread dispatch necessary indicator.
* Beagle: GPIO support (for BBB)Ketul Shah2015-08-181-0/+168
| | | | GPIO Driver Development for BeagleBone Black based on the generic GPIO API
* bsp/mpc83xx: Update due to header guard changeSebastian Huber2015-07-172-6/+6
| | | | Close #2373.
* bsps/powerpc: Provide debug and trace symbolsSebastian Huber2015-07-081-0/+3
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* score: Simplify <rtems/system.h>Sebastian Huber2015-06-264-0/+4
| | | | | Drop the <rtems/score/percpu.h> include since this file exposes a lot of implementation details.
* score: Add Thread_Control::is_fpSebastian Huber2015-06-091-17/+1
| | | | | | | | Store the floating-point unit property in the thread control block regardless of the CPU_HARDWARE_FP and CPU_SOFTWARE_FP settings. Make sure the floating-point unit is only enabled for the corresponding multilibs. This helps targets which have a volatile only floating point context like SPARC for example.
* bsps/powerpc: Fix potential integer overflowSebastian Huber2015-05-291-1/+1
| | | | Update #2356.
* beagle bsp: RTC support for BBBragunath2015-05-282-0/+26
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* arm/s3c24xx/clock/clockdrv.c: Remove unused variable warningJoel Sherrill2015-05-211-1/+0
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* arm/lpc22xx/clock/clockdrv.c: Remove unused variable warningJoel Sherrill2015-05-211-1/+0
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* bsps: Convert clock drivers to use a timecounterAlexander Krutwig2015-05-206-122/+80
| | | | Update #2271.
* bsps/sparc: Use inline functions for cache managerSebastian Huber2015-04-273-46/+32
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* bsps/cache: Clarify range functions supportSebastian Huber2015-04-272-4/+6
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* Fix broken BSPs due to a shared cache function declaration.Hesham ALMatary2015-04-271-1/+0
| | | | | Get rid of _CPU_cache_invalidate_instruction_range declaration as it doesn't make sense here.
* score: Refactor SMP cache manager supportSebastian Huber2015-04-201-172/+51
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* Replace www.rtems.com with www.rtems.orgSebastian Huber2015-03-202-2/+2
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* rtems: Use atomic operation with correct typeDaniel Cederman2015-03-201-1/+1
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* libcpu/bfin/clock/rtc.c: Do not use rtems_clock_get()Joel Sherrill2015-03-171-2/+2
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* libcpu/powerpc/mpc8260/console-generic/console-generic.c: Include bsp.h to ↵Joel Sherrill2015-03-091-3/+1
| | | | fix warning
* sparc64: fix copyright notices.Gedare Bloom2015-02-232-14/+4
| | | | | The sparc64 port had some incorrect copyright notices affixed to source code files.
* bsps/powerpc: Fix a clock driverNick Withers2015-01-301-9/+57
| | | | | | | PowerPC Book E: Account for an extra tick period if a tick increment's pending. Close #2230.
* bsps/powerpc: Fix switch statement in CPU identSebastian Huber2015-01-231-0/+2
| | | | Close #2237.
* powerpc: Fix AltiVec VSCR save/restoreSebastian Huber2015-01-201-4/+6
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* libcpu/powerpc/mpc6xx/mmu/bat.c: Now compiles with gcc 5.xJoel Sherrill2015-01-131-12/+12
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* powerpc: AltiVec and FPU context supportSebastian Huber2015-01-137-12/+821
| | | | | | | | | | | Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size.
* bsps/powerpc: Use e500 exc categories for e6500Sebastian Huber2015-01-131-0/+1
| | | | This is not correct, but works for now.
* powerpc: Use PPC_HAS_FPUSebastian Huber2015-01-091-6/+6
| | | | Provide floating point context support only if PPC_HAS_FPU == 1.
* powerpc: Set PPC_DEFAULT_CACHE_LINE_SIZE for e6500Sebastian Huber2015-01-091-15/+11
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* powerpc: Use PPC_DEFAULT_CACHE_LINE_SIZESebastian Huber2015-01-091-8/+2
| | | | | Use it for the default PPC_CACHE_ALIGNMENT. Use it for PPC_STRUCTURE_ALIGNMENT.
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