| Commit message (Collapse) | Author | Age | Files | Lines |
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The _CPU_Context_switch() is a normal function call. The following
registers are volatile (the caller must assume that the register
contents are destroyed by the callee) according to "SYSTEM V APPLICATION
BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0,
o1, o2, o3, o4, o5. Drop these registers from the context.
Ensure that offset defines match the structure offsets.
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The expression "*pi++" post-increments the pointer (not the value).
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Delete _CPU_Context_switch_to_first_task_smp() and use
_CPU_Context_restore() instead.
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Avoid usage of the same stack area by multiple secondary processors at
the same time.
Avoid magic delay loops.
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This may increase the cache hit performance.
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Add doxygen to the header files in sparc/shared/include directory.
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Add doxygen to the header files in sparc/shared/include directory.
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sparc/shared/startup/bspgetworkarea.c
* refactored sparc/shared/bspgetworkarea.c to sparc/shared/startup/bspgetworkarea.c
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_CPU_Context_switch_to_first_task_smp() branches to
done_flushing which requires o3 to be initalized with
"self per-CPU control", this adds initialization of
o3. This problem only affects SMP, see commit
f8ad6c6f7f8b591e were usage of o3 was intruduced.
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There is no point having interrupts enabled before reaching
boot_card() that disables interrupt. We better have it off
all the time.
It is required to turn off interrupt on secondary CPUs in an
SMP system.
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Basically the shared-irq handler overwrite the SMP/MP traphandler
previously initialized with set_vector(). That caused IPIs to enter
BSP spurious handler.
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This reduces the size of the RTEMS tests on average about 45%.
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This variable must be available for each processor in the system.
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Move the _CPU_Context_switch(), _CPU_Context_restore() and
_CPU_Context_switch_to_first_task_smp() code since the method to obtain
the processor index is BSP specific.
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Interrupt support for SMP and per-CPU thread dispatch disable level.
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As a side-effect the PR2082 is fixed with this and later changes.
The commit restores the _ISR_Handler code to the original version in
"cpukit/score/sparc/cpu_asm.S" in commit
6d42b4c60a4ac686489b793d5df2047c735c7c94. A list of reverted changes
follows.
commit c236082873cb4a2fd42af4ca0868106e1dd65422
Author: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Tue Jul 30 15:54:53 2013 +0200
smp: Provide cache optimized Per_CPU_Control
Delete _Per_CPU_Information_p.
This commit was completely reverted.
commit e517714b7cd28807aad4c1afd8c97df72dadb4c1
Author: Jennifer Averett <jennifer.averett@oarcorp.com>
Date: Tue Feb 26 12:31:23 2013 -0600
sparc: Remove dead code that was leftover from SMP development.
This commit was completely reverted.
commit 47a61aa16f81588f8ffb8ea5cfd1ceba3e9a867a
Author: Joel Sherrill <joel.sherrill@OARcorp.com>
Date: Fri Oct 7 14:35:03 2011 +0000
2011-10-07 Daniel Hellstrom <daniel@gaisler.com>
PR 1933/cpukit
* shared/irq_asm.S: From code inspection I have found the following
issues (most SMP), and some improvements in irq_asm.S. I would need a
long test with interrupts to verify the interrupt handler better,
however I can not see that these patches hurt. Please see comment per
hunk below, One should go through the file to indent delay-slots
correctly, I have fixed some in the patch areas. An extra space is
added in front of delay slots to indicate a delay slot.
This commit was completely reverted.
commit 0bd3f7e5d12fdbfb5bf4aa4a4169c67bfd92c988
Author: Jennifer Averett <Jennifer.Averett@OARcorp.com>
Date: Thu Jul 28 17:33:07 2011 +0000
2011-07-28 Jennifer Averett <Jennifer.Averett@OARcorp.com>
PR 1801
* shared/irq_asm.S: Modifications to synch the sparc with the smp
working tree.
This commit was completely reverted.
commit 5d69cd33e9a72cf8c1a24fc9eda7f64d61f10fd1
Author: Joel Sherrill <joel.sherrill@OARcorp.com>
Date: Wed Mar 16 20:05:30 2011 +0000
2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com>
PR 1729/cpukit
* shared/irq_asm.S: New file.
The parts modifying the original code of _ISR_Handler were reverted.
Only the content move remains.
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Delete _Per_CPU_Information_p.
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This is declared in <bsp/bootcard.h> and is the usual function to reset
a board.
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The bsp_fatal_extension() will call BSP_fatal_return().
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The work areas (RTEMS work space and C program heap) will be initialized
now in a separate step and are no longer part of
rtems_initialize_data_structures(). Initialization is performed with
tables of Heap_Area entries. This allows usage of scattered memory
areas present on various small scale micro-controllers.
The sbrk() support API changes also. The bsp_sbrk_init() must now deal
with a minimum size for the first memory chunk to take the configured
work space size into account.
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+ libbsp/sparc/shared/include/pci.h was largely a copy of
an older version of the cpukit pci.h. Removed much of the
contents and included <rtems/pci.h>.
+ sparc/*/pci*.c - Move to <rtems/pci.h> required updating
to use uint32_t for dword accesses.
+ Rename PCI_MULTI_FUNCTION to PCI_HEADER_TYPE_MULTI_FUNCTION
+ Define PCI_HEADER_TYPE_MULTI_FUNCTION in cpukit pci.h and remove
PCI_MULTI_FUNCTION definitions in C files.
+ Move PCI_INVALID_VENDORDEVICEID definitions from various C files
to cpukit pci.h
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Some register layout definitions for LEON3 reside in ambapp.h which
does not really has anything to do with device registers. The
register structures has been incorrectly named LEON3_*, the cores
are not only used on LEON3 but on LEON4 and perhaps on LEON5 when
that day comes. Some structures has been renamed according to the
GRLIB core name instead, which CPU that actually use it is not
relevant. Drivers has been updated with the new names.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
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The drivers are updated to use the new AMBA layer, however the
backwards-compatibility interface (ambapp_old) is used.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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The old layer had some limitations/problems for multiple AHB
buses since the data structure containing all AMBA devices
were allocated before scanning.
The new layer create devices as they are found and memory is
allocated using malloc() or bsp_early_malloc() during booting.
The old 8 functions for finding a specific AHB-Slave or
APB-Slave device has been replaced with one function,
ambapp_for_each(), which iterates over all devices matching
the specified search options and calls a user provided
function. The new way lowers the footprint and makes searching
more flexible.
The frequency information is now supported, if the frequency
of one device is reported by the user.
More AHB-to-AHB bridges are supported.
The API has been split into several parts in order to lower the
footprint.
The API also introduces the AMBAPP CORE concept, where one
ambapp_core can be created from one AHB Master, AHB Slave
and one APB Slave, at least one device is required for creating
a core.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
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The implementation use IRQ number instead of vector number since
some IRQs does not have a unique vector, for example the extended
interrupts all enter the same trap vector entry.
Added support for the LEON3 extended interrupt controller when using
the shared IRQ layer.
ERC32 patches untested.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Regenerate
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