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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This function is only used by the raspberrypi BSP.
This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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Adjust build support files to new directory layout.
This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.
Use the following directories and files:
* bsps/shared/cache
* bsps/@RTEMS_CPU@/shared/cache
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c
Update #3285.
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Define __INSIDE_RTEMS_BSD_TCPIP_STACK__ in the network interface driver
source files to avoid some build system magic.
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A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.
This has at least seven problems:
* The make preinstall step itself needs time and disk space.
* Errors in header files show up in the build tree copy. This makes it
hard for editors to open the right file to fix the error.
* There is no clear relationship between source and build tree header
files. This makes an audit of the build process difficult.
* The visibility of all header files in the build tree makes it
difficult to enforce API barriers. For example it is discouraged to
use BSP-specifics in the cpukit.
* An introduction of a new build system is difficult.
* Include paths specified by the -B option are system headers. This
may suppress warnings.
* The parallel build had sporadic failures on some hosts.
This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.
The new cpukit include directories are:
* cpukit/include
* cpukit/score/cpu/@RTEMS_CPU@/include
* cpukit/libnetworking
The new BSP include directories are:
* bsps/include
* bsps/@RTEMS_CPU@/include
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include
There are build tree include directories for generated files.
The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.
The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.
Update #3254.
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Updates #3520.
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It seems that the DWT CYCCNT does not advance when the CPU waits on a
WFI instruction.
That leads to the effect that for example on the atsamv BSP a sleep(1)
needs something in the range of a few minutes (depending on the
configured systick). A debugger might disables some deep sleep modes so
that the problem only appears if the application is executed without a
debugger.
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Update #3090.
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Remove old ISR parameter since is not used by the clock driver shell.
Make an implementation optional.
Update #3139.
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The BSP_output_char should output a char and not mingle with high level
processing, e.g. '\n' to '\r\n' translation. Move this translation to
rtems_putc(). Remove it from all the BSP_output_char implementations.
Close #3122.
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Update #2133.
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Update #3090.
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Update #3071.
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Close #3071.
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Change bsp_interrupt_vector_enable() and bsp_interrupt_vector_disable()
to not return a status code. Add bsp_interrupt_assert() and use it to
validate the vector number in the vector enable/disable implementations.
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According to manual, the used operations (Clean Line by PA, Clean and
Invalidate Line by PA, Cache Sync) are atomic and do not require
locking.
Update #3007.
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Enable/disable vector routines now check for a valid vector. Without
these guards, the enable/disable vector routines will not work with the
interrupt server.
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Update #3002.
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It is necessary to enable the DWT using a special initialization
sequence before the CYCCNT can be enabled. See for example the
RESET_CYCLE_COUNTER in libbsp/arm/atsam/utils/utility.h.
Note that this problem only occurs if no debugger is connected. A
debugger most likely already enables the necessary module.
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Use the previously unused TPIDRPRW register to get the per-CPU control
of the current processor. This avoids instructions in
GET_SELF_CPU_CONTROL which are not available in Thumb mode.
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The symbol can be used by bsp_start_hook_0 when complete
RAM memory is initialization and overwritten during BSP
self-test. The test overwrites even memory used to store
return address / link register and regular resturn from
bsp_start_hook_0 is not possible then.
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Protection by rtems_interrupt_disable() is incompatible with SMP build.
Actual page table entries manipulation function does not need locking
and disabling cache and can be run concurrently even on multiple
CPUs as long as changes do not modify same region. If the function
is called from more threads/CPUs to modify same region with different
mapping options concurrently then there is problem at another level
of virtual address space management and has to be solved by mutex
or other locking at that level.
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This lets the table be changed at runtime for dynamic loading and
debugger support.
Closes #2775.
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architecture variants now.
Next cache operations should work on most of cores now
rtems_cache_flush_entire_data()
rtems_cache_invalidate_entire_data()
rtems_cache_invalidate_entire_instruction()
Instruction cache invalidate works on the first level for now only.
Data cacache operations are extended to ensure flush/invalidate
on all cache levels.
The CP15 arm_cp15_data_cache_clean_all_levels() function extended
to continue through unified levels too (ctype = 4).
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Disabling MMU requires complex cache flushing and invalidation
operations. There is almost no way how to do that right
on SMP system without stopping all other CPUs. On the other hand,
there is documented sequence of operations which should be used
according to ARM manual and it guarantees even distribution
of maintenance operations to other cores for last generation
of Cortex-A cores with multiprocessor extension.
This change could require addition of appropriate entry
to arm_cp15_start_mmu_config_table for some BSPs to ensure
that MMU table stays accessible after MMU is enabled
{
.begin = (uint32_t) bsp_translation_table_base,
.end = (uint32_t) bsp_translation_table_base + 0x4000,
.flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
}
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