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* bsps/arm: Convert PL011 and PL050 console driversSebastian Huber2014-10-144-110/+98
| | | | Use Termios device API.
* bsps/arm: Move abort stackSebastian Huber2014-10-131-4/+4
| | | | | Move abort stack above the other exception stacks to use them just in case.
* arm/shared/abort/abort.c: Fix warnings and clean upJoel Sherrill2014-10-091-17/+28
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* bsps/arm: Add a9mpcore_clock_initialize_early()Sebastian Huber2014-09-102-5/+10
| | | | | This is necessary to use the CPU counter converter even in case no clock driver is present, e.g. in tmcontext01.
* bsps/arm: Fix get cache sizeSebastian Huber2014-09-101-4/+6
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* bsps/arm: Fix invalidate instruction cacheSebastian Huber2014-09-101-33/+2
| | | | | | | Do not invalidate the entire L2 cache since it is a uniform cache in _CPU_cache_invalidate_entire_instruction(). For consitency do not touch the L2 cache even for the range function _CPU_cache_invalidate_instruction_range().
* bsps/arm: Fix GIC tm27 supportSebastian Huber2014-09-101-15/+29
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* arm: Add support for FPv4-SP floating point unitSebastian Huber2014-08-121-0/+15
| | | | | This floating point unit is available in Cortex-M4 processors and defined by ARMv7-M. This adds basic support for other VFP-D16 variants.
* Common ARM A8 code.Chris Johns2014-07-161-0/+55
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* bsps/arm: Rename bsp_mm_config_tableSebastian Huber2014-07-012-4/+6
| | | | | | Rename bsp_mm_config_table to arm_cp15_start_mmu_config_table and rename bsp_mm_config_table_size to arm_cp15_start_mmu_config_table_size to be in line with the other names in <bsp/arm-cp15-start.h>.
* bsps/arm: Fix Cortex-A9 MPCore clock driverSebastian Huber2014-06-061-9/+18
| | | | | | The nanoseconds extension returned wrong values on secondary processors since some of the global timer registeres are banked. Use global variables instead.
* bsps/arm: Change L2 cache initializationSebastian Huber2014-06-062-50/+1
| | | | | Do not touch the L1 caches since they have been initialized by the start hooks.
* bsps/arm: Define ARM_CP15_TEXT_SECTIONSebastian Huber2014-06-063-43/+5
| | | | | Define ARM_CP15_TEXT_SECTION to BSP_START_TEXT_SECTION so that the start code is in the right section.
* bsps/arm: Simplify L1 caches supportSebastian Huber2014-06-051-55/+12
| | | | Delete superfluous/incorrect interrupt disable/enable.
* bsps/arm: Cortex-A9 MPCore startSebastian Huber2014-06-051-0/+5
| | | | Invalidate entire branch predictor array.
* bsps/arm: Cortex-A9 MPCore startSebastian Huber2014-06-051-4/+4
| | | | Enable SCU only on the boot processor.
* bsps/arm: Cortex-A9 MPCore startSebastian Huber2014-06-051-6/+13
| | | | Add arm_a9mpcore_start_enable_smp_in_auxiliary_control().
* bsps/arm: Simplify Cortex-A9 MPCore startSebastian Huber2014-06-051-31/+32
| | | | | Add arm_a9mpcore_start_on_secondary_processor(). Rely on error checks in _SMP_Start_multitasking_on_secondary_processor().
* bsp/arm: Broadcast cache maintenancesRalf Kirchner2014-05-281-1/+1
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* bsps/arm: Declare return typesSebastian Huber2014-05-071-7/+8
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* bsps: Fix TLS support in linker command filesSebastian Huber2014-04-221-1/+3
| | | | | The TLS section symbols had wrong values in case of an empty TLS data section and a nonempty TLS BSS section.
* bsp/arm: Cleanup L2 cache handlingRalf Kirchner2014-04-171-38/+7
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* bsp/arm: Correct L2 cache enable methodRalf Kirchner2014-04-171-53/+48
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* bsp/arm: Add cache size methodsRalf Kirchner2014-04-172-0/+115
| | | | Add new methods which deliver the cache sizes of for supported cache levels.
* bsp/arm: Add L2 cache lockingRalf Kirchner2014-04-171-9/+34
| | | | This level 2 cache is a shared data and instruction cache and thus needs locking.
* bsp/arm: Remove unused cache store methodsRalf Kirchner2014-04-172-30/+0
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* bsp/arm: Correct cache misalignment handlingRalf Kirchner2014-04-172-32/+60
| | | | Correct misalignment handling and prepare for locking.
* bsp/arm: Correct L2 cache flushingRalf Kirchner2014-04-171-17/+31
| | | | Correct misalignment handling and prepare for locking.
* bsp/arm: Remove arm erratum 764369 from L2 cacheRalf Kirchner2014-04-171-14/+0
| | | | Arm erratum 764369 only applies to the level 1 cache.
* bsp/arm: Consistenly same handling for flushingRalf Kirchner2014-04-171-2/+2
| | | | | It is importeant to consistently apply the same handling for flushing within level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
* bsp/arm: RTEMS_SMP to arm erratum 764369 detectionRalf Kirchner2014-04-173-10/+8
| | | | Move the RTEMS_SMP conditional compilation to the detection method of arm erratum 764369
* bsp/arm: Erratum 764369 after enabling SCURalf Kirchner2014-04-171-1/+1
| | | | Execute the SCU part of the workaround of arm erratum 764368 after the SCU was enabled.
* bsp/arm: Correct detection of arm erratum 764368Ralf Kirchner2014-04-171-0/+1
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* bsp/arm: Cleanup L1 cacheRalf Kirchner2014-04-171-2/+2
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* score: SMP initialization changesSebastian Huber2014-04-141-15/+26
| | | | | | | | | | | | | | | | | Add and use _CPU_SMP_Start_processor(). Add and use _CPU_SMP_Finalize_initialization(). This makes most _CPU_SMP_Initialize() functions a bit simpler since we can calculate the minimum value of the count of processors requested by the application configuration and the count of physically or virtually available processors in the high-level code. The CPU port has now the ability to signal a processor start failure. With the support for clustered/partitioned scheduling the presence of particular processors can be configured to be optional or mandatory. There will be a fatal error only in case mandatory processors are not present. The CPU port may use a timeout to monitor the start of a processor.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-2146-46/+46
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* bsps/arm: Add DP83848 PHY support to LPC EthernetPavel Pisa2014-03-141-0/+8
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* bsps/arm: Add PHY detection to LPC EthernetPavel Pisa2014-03-141-13/+45
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* bsps/arm: Reset MII management in LPC EthernetPavel Pisa2014-03-141-1/+7
| | | | Reduce MII clock to support LPC17XX.
* bsp/arm: Add handling for level 2 L2C-310 cache controllerRalf Kirchner2014-03-132-0/+1998
| | | | | | arm-l2c-310/cache_.h contains the handling for the L2C-310 level 2 cache controller from arm. It references the arm level 1 cache handling in the new file arm-cache-l1.h.
* bsp/arm: Add SCU errata handling for L2C-310 cacheRalf Kirchner2014-03-132-10/+36
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* bsp/arm: Add arm-errata.h and arm-release-id.hRalf Kirchner2014-03-132-0/+279
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* bsp/arm: Add linker symbol bsp_processor_countRalf Kirchner2014-03-131-0/+2
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* bsp/arm: Separate setup for translation tableRalf Kirchner2014-03-131-4/+20
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* bsp/arm: Invalidate SCURalf Kirchner2014-03-132-1/+25
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* bsp/arm: SMP support for a9mpcore_clock_cleanup()Ralf Kirchner2014-03-131-4/+18
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* bsp/arm: Avoid warningRalf Kirchner2014-03-131-0/+1
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* score: Rename rtems_smp_process_interrupt()Sebastian Huber2014-02-192-5/+4
| | | | | | Rename rtems_smp_process_interrupt() into _SMP_Inter_processor_interrupt_handler(). Delete unused header file <rtems/bspsmp.h>.
* score: Rename rtems_smp_secondary_cpu_initialize()Sebastian Huber2014-02-191-1/+2
| | | | | | Rename rtems_smp_secondary_cpu_initialize() into _SMP_Start_multitasking_on_secondary_processor(). Move declaration to <rtems/score/smpimpl.h>.
* score: Delete bsp_smp_broadcast_interrupt()Sebastian Huber2014-02-191-12/+0
| | | | | | Since the per-CPU SMP lock must be acquired and released to send the message a single interrupt broadcast operations offers no benefits. If synchronization is required, then a SMP barrier must be used anyway.
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