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Commit message (
Expand
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Author
Age
Files
Lines
*
bsps/arm: Fix bit field offset in GIC support
Sebastian Huber
2017-05-11
1
-1
/
+1
*
libbsp/arm: Add the TTB table to the default MMU set up as read/write.
Chris Johns
2016-08-15
1
-0
/
+4
*
arm/bsps: CP15 and basic cache support entire cache clean for more architectu...
Pavel Pisa
2016-07-20
1
-1
/
+5
*
bsps/arm: basic on core cache support changed to use l1 functions.
Pavel Pisa
2016-07-04
1
-42
/
+29
*
bsps/arm: Support recent bootloaders starting kernel in HYP mode
Pavel Pisa
2016-07-04
2
-2
/
+15
*
bsps: Add defines for some linker subsections
Sebastian Huber
2016-05-31
1
-1
/
+7
*
score: Distribute clock tick to all online CPUs
Sebastian Huber
2016-03-04
1
-0
/
+5
*
bsp/atsam: New
Sebastian Huber
2016-01-19
1
-0
/
+39
*
bsps/arm: Fix broken switch statement
Sebastian Huber
2016-01-18
1
-3
/
+4
*
bsps: Generalize .nocacheheap to .nocachenoload
Sebastian Huber
2015-10-28
2
-2
/
+8
*
bsps/arm: Add missing translation table entry
Sebastian Huber
2015-10-14
1
-0
/
+4
*
bsps: Add .nocacheheap section
Sebastian Huber
2015-10-08
1
-5
/
+5
*
bsps/arm: Fix function definition
Sebastian Huber
2015-09-04
1
-1
/
+1
*
bsps/arm: Do not use __ARM_ARCH_7A__
Sebastian Huber
2015-07-31
1
-28
/
+16
*
bsps/arm: Update due to API changes
Sebastian Huber
2015-07-21
1
-4
/
+4
*
bsps/arm: Add .nocache section
Sebastian Huber
2014-11-27
2
-1
/
+17
*
bsps/arm: L1 cache support changes
Sebastian Huber
2014-11-20
1
-16
/
+21
*
bsps/arm: Convert PL011 and PL050 console drivers
Sebastian Huber
2014-10-14
2
-6
/
+28
*
bsps/arm: Add a9mpcore_clock_initialize_early()
Sebastian Huber
2014-09-10
1
-1
/
+10
*
bsps/arm: Fix GIC tm27 support
Sebastian Huber
2014-09-10
1
-15
/
+29
*
Common ARM A8 code.
Chris Johns
2014-07-16
1
-0
/
+55
*
bsps/arm: Rename bsp_mm_config_table
Sebastian Huber
2014-07-01
1
-2
/
+4
*
bsps/arm: Change L2 cache initialization
Sebastian Huber
2014-06-06
1
-47
/
+0
*
bsps/arm: Define ARM_CP15_TEXT_SECTION
Sebastian Huber
2014-06-06
2
-42
/
+1
*
bsps/arm: Simplify L1 caches support
Sebastian Huber
2014-06-05
1
-55
/
+12
*
bsps/arm: Cortex-A9 MPCore start
Sebastian Huber
2014-06-05
1
-0
/
+5
*
bsps/arm: Cortex-A9 MPCore start
Sebastian Huber
2014-06-05
1
-4
/
+4
*
bsps/arm: Cortex-A9 MPCore start
Sebastian Huber
2014-06-05
1
-6
/
+13
*
bsps/arm: Simplify Cortex-A9 MPCore start
Sebastian Huber
2014-06-05
1
-31
/
+32
*
bsp/arm: Broadcast cache maintenances
Ralf Kirchner
2014-05-28
1
-1
/
+1
*
bsps/arm: Declare return types
Sebastian Huber
2014-05-07
1
-7
/
+8
*
bsp/arm: Add cache size methods
Ralf Kirchner
2014-04-17
1
-0
/
+33
*
bsp/arm: Remove unused cache store methods
Ralf Kirchner
2014-04-17
1
-9
/
+0
*
bsp/arm: Correct cache misalignment handling
Ralf Kirchner
2014-04-17
1
-6
/
+6
*
bsp/arm: Consistenly same handling for flushing
Ralf Kirchner
2014-04-17
1
-2
/
+2
*
bsp/arm: RTEMS_SMP to arm erratum 764369 detection
Ralf Kirchner
2014-04-17
3
-10
/
+8
*
bsp/arm: Erratum 764369 after enabling SCU
Ralf Kirchner
2014-04-17
1
-1
/
+1
*
bsp/arm: Correct detection of arm erratum 764368
Ralf Kirchner
2014-04-17
1
-0
/
+1
*
bsp/arm: Cleanup L1 cache
Ralf Kirchner
2014-04-17
1
-2
/
+2
*
Change all references of rtems.com to rtems.org.
Chris Johns
2014-03-21
17
-17
/
+17
*
bsp/arm: Add handling for level 2 L2C-310 cache controller
Ralf Kirchner
2014-03-13
1
-0
/
+483
*
bsp/arm: Add SCU errata handling for L2C-310 cache
Ralf Kirchner
2014-03-13
2
-10
/
+36
*
bsp/arm: Add arm-errata.h and arm-release-id.h
Ralf Kirchner
2014-03-13
2
-0
/
+279
*
bsp/arm: Add linker symbol bsp_processor_count
Ralf Kirchner
2014-03-13
1
-0
/
+2
*
bsp/arm: Separate setup for translation table
Ralf Kirchner
2014-03-13
1
-4
/
+20
*
bsp/arm: Invalidate SCU
Ralf Kirchner
2014-03-13
2
-1
/
+25
*
score: Rename rtems_smp_process_interrupt()
Sebastian Huber
2014-02-19
1
-1
/
+0
*
score: Rename rtems_smp_secondary_cpu_initialize()
Sebastian Huber
2014-02-19
1
-1
/
+2
*
bsps/arm: Use Global Timer for Cortex-A9 MPCore
Sebastian Huber
2014-02-10
2
-4
/
+23
*
bsps/arm: Use ALIGN_WITH_INPUT
Sebastian Huber
2014-01-13
2
-13
/
+0
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