| Commit message (Collapse) | Author | Age | Files | Lines |
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* rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
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* rtems/score/cpu.h: IDLE task should not be FP. This was a mistake
in the previous patch that has now been confirmed.
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* cpu.c: Enhancements and fixes for modifying the SR when changing
the interrupt level.
* cpu_asm.S: Fixed handling of FP enable bit so it is properly
managed on a per-task basis, improved handling of interrupt levels,
and made deferred FP contexts work on the MIPS.
* rtems/score/cpu.h: Modified to support above changes.
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* rtems/Makefile.am: Removed.
* rtems/score/Makefile.am: Removed.
* configure.ac: Reflect changes above.
* Makefile.am: Reflect changes above.
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* asm.h: Remove #include <rtems/score/targopts.h>.
Add #include <rtems/score/cpuopts.h>.
* configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
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* configure.ac: Use RTEMS_ENV_RTEMSCPU.
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* Makefile.am: Add multilib support.
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This was tracked as PR91.
* rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
is used to specify if the port uses the standard macro for this (FALSE).
A TRUE setting indicates the port provides its own implementation.
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* cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
compilation block with (CPU_HARDWARE_FP == FALSE). Reported by
Wayne Bullaughey <wayne@wmi.com>.
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* .cvsignore: Add autom4te.cache for autoconf > 2.52.
* configure.in: Remove.
* configure.ac: New file, generated from configure.in by autoupdate.
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* rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
* Makefile.am: Use 'PREINSTALL_FILES ='.
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* cpu.c: Fixed typo.
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* rtems/score/mips.h: Added constants for MIPS exception numbers.
All exceptions should be given low numbers and thus can be installed
and processed in a uniform manner. Variances between various MIPS
ISA levels were not accounted for.
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* rtems/score/mips.h: Added constants for MIPS exception numbers.
All exceptions should be given low numbers and thus can be installed
and processed in a uniform manner. Variances between various MIPS
ISA levels were not accounted for.
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* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
* cpu_asm.S: Now works on Mongoose-V. Missed in previous patch.
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* rtems/score/cpu.h: Add the interrupt stack structure and enhance
the context initialization to account for floating point tasks.
* rtems/score/mips.h: Added the routines mips_set_cause(),
mips_get_fcr31(), and mips_set_fcr31().
* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
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* cpu_asm.S: Merged patches from Gregory Menke
<Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
stack usage and include nops in the delay slots.
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* cpu_asm.S: Added code to save and restore SR and EPC to
properly support nested interrupts. Note that the ISR
(not RTEMS) enables interrupts allowing the nesting to occur.
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* cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
Removed unused variable _CPU_Thread_dispatch_pointer
and cleaned numerous comments.
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* cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
Also reimplemented some assembly routines in C further reducing
the amount of assembly and increasing maintainability.
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* Makefile.am, rtems/score/Makefile.am:
Apply include_*HEADERS instead of H_FILES.
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* rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
register constraints from "general" to "register".
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* cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
to make it easier to conditionalize the code for various ISA levels.
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* idtcpu.h: Commented out definition of "wait". It was stupid to
use such a common word as a macro.
* rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
* rtems/score/mips.h: Added include of <idtcpu.h>.
* rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
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* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
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* cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
Previous code resulting in the interrupted immediately returning
to the caller of the routine it was inside.
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* cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
because it has not been allocated yet.
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* cpu.c: Removed duplicate declaration for _ISR_Vector_table.
* cpu_asm.S: Removed assembly language to vector ISR handler
on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP.
* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
longer a constant -- get the real value from libcpu.
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* cpu_asm.h: Removed.
* Makefile.am: Remove cpu_asm.h.
* rtems/score/mips64orion.h: Renamed mips.h.
* rtems/score/mips.h: New file, formerly mips64orion.h.
Header rewritten.
(mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
mips_disable_in_interrupt_mask): New macros.
* rtems/score/Makefile.am: Reflect renaming mips64orion.h.
* asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
few defines that were in <cpu_asm.h>.
* cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
MIPS ISA 3 is still in assembly for now.
(_CPU_Thread_Idle_body): Rewrote in C.
* cpu_asm.S: Rewrote file header.
(FRAME,ENDFRAME) now in asm.h.
(_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
(_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
(_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
leaves other bits in SR alone on task switch.
(mips_enable_interrupts,mips_disable_interrupts,
mips_enable_global_interrupts,mips_disable_global_interrupts,
disable_int, enable_int): Removed.
(mips_get_sr): Rewritten as C macro.
(_CPU_Thread_Idle_body): Rewritten in C.
(init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
placed in libcpu.
(exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
to libcpu/mips/shared/interrupts.
(general): Cleaned up comment blocks and #if 0 areas.
* idtcpu.h: Made ifdef report an error.
* iregdef.h: Removed warning.
* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
number defined by libcpu.
(_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
to access SR.
(_CPU_ISR_Set_level): Rewritten as macro for ISA I.
(_CPU_Context_Initialize): Honor ISR level in task initialization.
(_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
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* rtems/score/cpu.h: When mips ISA level is 1, registers in the
context should be 32 not 64 bits.
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* cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
correct name of _CPU_Context_switch_restore. Added dummy
version of exc_utlb_code() so applications would link.
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* Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
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* Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
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* Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
Switch to GNU canonicalization.
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Joel Sherrill <joel@OARcorp.com>
* This is a major reworking of the mips64orion port to use
gcc predefines as much as possible and a big push to multilib
the mips port. The mips64orion port was copied/renamed to mips
to be more like other GNU tools. Alan did most of the technical
work of determining how to map old macro names used by the mips64orion
port to standard compiler macro definitions. Joel did the merge
with CVS magic to keep individual file history and did the BSP
modifications. Details follow:
* Makefile.am: idtmon.h in mips64orion port not present.
* asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
* cpu.c: Comments added.
* cpu_asm.S: Conditionals changed. MIPS ISA level 1 support added.
First attempt at exception/interrupt processing for ISA level 1
and minus any use of IDT/MON added.
* idtcpu.h: Conditionals changed to use gcc predefines.
* iregdef.h: Ditto.
* cpu_asm.h: No real change. Merger required commit.
* rtems/Makefile.am: Ditto.
* rtems/score/Makefile.am: Ditto.
* rtems/score/cpu.h: Change MIPS64ORION to MIPS.
* rtems/score/mips64orion.h: Change MIPS64ORION to MIPS. Convert
from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
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* Makefile.am: Include compile.am.
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a BSP (c4xsim) supporting the simulator included with gdb. This port
was done by Joel Sherrill and Jennifer Averett of OAR Corporation.
Also included with this port is a space/time optimization to eliminate
FP context switch management on CPUs without hardware or software FP.
An issue with this port was that sizeof(unsigned32) = sizeof(unsigned8)
on this CPU. This required addressing alignment checks and assumptions
as well as fixing code that assumed sizeof(unsigned32) == 4.
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that is another small step toward multilibs:
Changes:
* Eliminate RTEMS_CHECK_CUSTOM_BSP from all configure.ins below exec/
* Add RTEMS_CHECK_CUSTOM_BSP to the multilib-disabled branch in
RTEMS_ENV_RTEMSCPU to preserve the old per-BSP building scheme
functional.
Notes:
* --enable-multilibs is still non-functional
* This patch should not have any influence on the old building
scheme (--disable-multilib should silently fall back to the old
building scheme).
* running ./bootstrap is required after applying the patch
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that is a somewhat experimental, multilib-related patch:
Changes:
* Use RTEMS_ENV_RTEMSCPU instead of RTEMS_ENV_RTEMSBSP in
configure.ins below exec/.
At the moment, RTEMS_ENV_RTEMSCPU is more or less an optical change
to emphasize that these subdirectories shall not depend on RTEMS_BSP
than a real behavioral change.
* Add AC_DEFINE_* to several aclocal/*.m4 macros to prepare
autoheader/autoconf generated targopts.h and similiar configuration
headers.
* c/src/configure.in: remove exec from cfg_subdirs if multilibs are
enabled (c/src is build per bsp, exec shall be build per cpu in c/
or from the toplevel in future, when multilibs are enabled.)
Notes:
* This patch should not have any impact on the current building scheme.
* --enable-multilib still does not work.
* running bootstrap from the toplevel directory is required.
CVS: ----------------------------------------------------------------------
CVS: Enter Log. Lines beginning with `CVS:' are removed automatically
CVS:
CVS: Committing in .
CVS:
CVS: Modified Files:
CVS: c/src/tests/libtests/termios/init.c
CVS: ----------------------------------------------------------------------
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_Interrupt_Manager_initialization.
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adds .cvsignore.
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that contains:
* Removes remaining (now illegal) references to $(SRC) from a couple of
Makefile.ams
* Removes duplicate AC_CONFIG_SUBDIRS macro from c/configure.in
* Moves ENABLE_LIBCDIR into RTEMS_PROG_C[C|XX]_FOR_TARGET (hides LIBCDIR
from most configure scripts, i.e. LIBCDIR becomes less visible)
* Adds RTEMS_PROG_C[C|XX]_FOR_TARGET and RTEMS_CANONICALIZE_TOOLS to
libbsp/*/configure.ins (A minor bug in previous implementations, which
only has an impact when switching to GNU/Cygnus canonicalization)
* Cleans up several bogus comments.
* Removes MKLIB
* Switches the version number to 4.5.0 (for testing version number
handling)
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Ralf Corsepius <corsepiu@faw.uni-ulm.de> that contain:
* Modifications, (minor) corrections, cleanups to most existing
Makefile.ams
* Adds automake support to all remaining BSPs which have not yet been
converted to automake.
* Makefile.am for all remaining wrapup/Makefile.ams
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that contains:
* cleanups to configuration files
* A reworked gccnewlib.spec.in: I have reformated it for enhanced
readability and added more rtems-base packages. It now should be free of
any installation conflicts (If there still remain some, they should be
regarded as bugs).
* A fix to the bin2boot RTEMS_BSP issue (make RTEMS_BSP="pc386 pc486"
now works).
* removes libbsp/bare/wrapup
* Further cleanups
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<corsepiu@faw.uni-ulm.de> which implements automake support for some
score/cpu/<RTEMS_CPU> subdirectories and fixes a few minor configuration
bugs.
To apply:
rm -rf c/src/exec/score/cpu/a29k/wrap
rm -rf c/src/exec/score/cpu/hppa1.1/wrap
rm -rf c/src/exec/score/cpu/i386/wrap
rm -rf c/src/exec/score/cpu/mips64orion/wrap
rm -rf c/src/exec/score/cpu/no_cpu/wrap
patch -p1 < rtems-rc-19991123-rc-2.diff.gz
Notes:
* I don't see a possiblity to convert the powerpc subdirectory in its
current layout to automake the time being.
* Besides the fact that this subdirectory is not in single-tree building
layout, the actual showstopper is the ifeq $(RTEMS_CPU_MODEL),mpc750)
gmake-conditional in powerpc/Makefile.in, which automake (correctly)
refuses to handle.
* The problem is *not* specific to the powerpc. Other CPUs basically
have similar problems (SH:sh7032 vs sh7045, SPARC: erc32.h in
score/cpu/sparc), but have been lucky to get around real issues (cf.
configuration files below score/cpu/sh/).
* From a configuration focused POV this problem boils down to a
file/subdirectory selection problem:
ppc: 1 or others
sh: 1 out of 2
sparc: 1 out of 1
Automake's means to implement such behavior is using conditionals to be
evaluated at configuration-time. The old configuration scheme however
used make-time conditionals. The SH port was lucky to get around this
issue because it applies a selection from a limited set of possible
selections, the powerpc however applies a selection from an unlimited
set, based on data not being available at configuration time.
* Currently I only see two general solutions:
1) make RTEMS_CPU_MODEL available at configuration time, ie. replace
make-time configuration by configuration-time configuration
2) Perform the selection at build-time, i.e. always install all files,
but use #ifdef #else #endif in source files. This is what the m68k has
exploited at other locations inside of the source-tree.
=> This directory is the last one remaining not using automake below the
whole exec/ hierarchy.
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<corsepiu@faw.uni-ulm.de> which implements automake support for some
score/cpu/<RTEMS_CPU> subdirectories and fixes a few minor configuration
bugs.
To apply:
rm -rf c/src/exec/score/cpu/a29k/wrap
rm -rf c/src/exec/score/cpu/hppa1.1/wrap
rm -rf c/src/exec/score/cpu/i386/wrap
rm -rf c/src/exec/score/cpu/mips64orion/wrap
rm -rf c/src/exec/score/cpu/no_cpu/wrap
patch -p1 < rtems-rc-19991123-rc-2.diff.gz
Notes:
* I don't see a possiblity to convert the powerpc subdirectory in its
current layout to automake the time being.
* Besides the fact that this subdirectory is not in single-tree building
layout, the actual showstopper is the ifeq $(RTEMS_CPU_MODEL),mpc750)
gmake-conditional in powerpc/Makefile.in, which automake (correctly)
refuses to handle.
* The problem is *not* specific to the powerpc. Other CPUs basically
have similar problems (SH:sh7032 vs sh7045, SPARC: erc32.h in
score/cpu/sparc), but have been lucky to get around real issues (cf.
configuration files below score/cpu/sh/).
* From a configuration focused POV this problem boils down to a
file/subdirectory selection problem:
ppc: 1 or others
sh: 1 out of 2
sparc: 1 out of 1
Automake's means to implement such behavior is using conditionals to be
evaluated at configuration-time. The old configuration scheme however
used make-time conditionals. The SH port was lucky to get around this
issue because it applies a selection from a limited set of possible
selections, the powerpc however applies a selection from an unlimited
set, based on data not being available at configuration time.
* Currently I only see two general solutions:
1) make RTEMS_CPU_MODEL available at configuration time, ie. replace
make-time configuration by configuration-time configuration
2) Perform the selection at build-time, i.e. always install all files,
but use #ifdef #else #endif in source files. This is what the m68k has
exploited at other locations inside of the source-tree.
=> This directory is the last one remaining not using automake below the
whole exec/ hierarchy.
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