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* 2002-03-13 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-03-151-22/+26
| | | | | | * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug. * rtems/score/cpu.h: Fixed register numbering in comments and made interrupt enable/disable more robust.
* 2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-03-082-1/+73
| | | | | | | | | | | | * cpu_asm.S: Added support for the debug exception vector, cleaned up the exception processing & exception return stuff. Re-added EPC in the task context structure so the gdb stub will know where a thread is executing. Should've left it there in the first place... * idtcpu.h: Added support for the debug exception vector. * cpu.c: Added ___exceptionTaskStack to hold a pointer to the stack frame in an interrupt so context switch code can get the userspace EPC when scheduling. * rtems/score/cpu.h: Re-added EPC to the task context.
* 2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-03-011-3/+16
| | | | | | | | | | | | | | | | * cpu_asm.S: Fixed exception return address, modified FP context switch so FPU is properly enabled and also doesn't screw up the exception FP handling. * idtcpu.h: Added C0_TAR, the MIPS target address register used for returning from exceptions. * iregdef.h: Added R_TAR to the stack frame so the target address can be saved on a per-exception basis. The new entry is past the end of the frame gdb cares about, so doesn't affect gdb or cpu.h stuff. * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it to obtain FPU defines without systax errors generated by the C defintions. * cpu.c: Improved interrupt level saves & restores.
* 2002-02-08 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-02-081-101/+105
| | | | | * iregdef.h, rtems/score/cpu.h: Reordered register in the exception stack frame to better match gdb's expectations.
* 2001-02-05 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-02-051-11/+132
| | | | | | | | | * cpu_asm.S: Enhanced to save/restore more registers on exceptions. * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every register individually and document when it is saved. * idtcpu.h: Added constants for the coprocessor 1 registers revision and status.
* 2001-02-05 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-02-052-0/+0
| | | | * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
* 2001-02-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-02-041-1/+1
| | | | | * rtems/score/cpu.h: IDLE task should not be FP. This was a mistake in the previous patch that has now been confirmed.
* 2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-02-011-19/+44
| | | | | | | | | * cpu.c: Enhancements and fixes for modifying the SR when changing the interrupt level. * cpu_asm.S: Fixed handling of FP enable bit so it is properly managed on a per-task basis, improved handling of interrupt levels, and made deferred FP contexts work on the MIPS. * rtems/score/cpu.h: Modified to support above changes.
* 2002-01-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2002-01-302-35/+0
| | | | | | | * rtems/Makefile.am: Removed. * rtems/score/Makefile.am: Removed. * configure.ac: Reflect changes above. * Makefile.am: Reflect changes above.
* 2001-11-28 Joel Sherrill <joel@OARcorp.com>,Joel Sherrill2001-11-281-0/+7
| | | | | | | This was tracked as PR91. * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which is used to specify if the port uses the standard macro for this (FALSE). A TRUE setting indicates the port provides its own implementation.
* 2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2001-09-271-1/+1
| | | | | * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. * Makefile.am: Use 'PREINSTALL_FILES ='.
* 2000-05-24 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-05-241-7/+38
| | | | | | | * rtems/score/mips.h: Added constants for MIPS exception numbers. All exceptions should be given low numbers and thus can be installed and processed in a uniform manner. Variances between various MIPS ISA levels were not accounted for.
* 2001-05-22 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2001-05-222-21/+78
| | | | | | | | * rtems/score/cpu.h: Add the interrupt stack structure and enhance the context initialization to account for floating point tasks. * rtems/score/mips.h: Added the routines mips_set_cause(), mips_get_fcr31(), and mips_set_fcr31(). * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
* 2001-03-14 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-03-144-55/+32
| | | | | | * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: Removed unused variable _CPU_Thread_dispatch_pointer and cleaned numerous comments.
* 2001-03-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-03-142-82/+71
| | | | | | | * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h: Merged MIPS1 and MIPS3 code reducing the number of lines of assembly. Also reimplemented some assembly routines in C further reducing the amount of assembly and increasing maintainability.
* 2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2001-02-051-3/+3
| | | | | * Makefile.am, rtems/score/Makefile.am: Apply include_*HEADERS instead of H_FILES.
* 2001-01-12 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-121-2/+2
| | | | | * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected register constraints from "general" to "register".
* 2001-01-09 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-092-1/+17
| | | | | * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants to make it easier to conditionalize the code for various ISA levels.
* 2001-01-08 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-082-3/+6
| | | | | | | | * idtcpu.h: Commented out definition of "wait". It was stupid to use such a common word as a macro. * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3. * rtems/score/mips.h: Added include of <idtcpu.h>. * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
* 2001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-031-1/+9
| | | | | * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
* 2000-12-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-131-1/+1
| | | | | | | | * cpu.c: Removed duplicate declaration for _ISR_Vector_table. * cpu_asm.S: Removed assembly language to vector ISR handler on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP. * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No longer a constant -- get the real value from libcpu.
* 2000-12-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-134-129/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * cpu_asm.h: Removed. * Makefile.am: Remove cpu_asm.h. * rtems/score/mips64orion.h: Renamed mips.h. * rtems/score/mips.h: New file, formerly mips64orion.h. Header rewritten. (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask, mips_disable_in_interrupt_mask): New macros. * rtems/score/Makefile.am: Reflect renaming mips64orion.h. * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the few defines that were in <cpu_asm.h>. * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine. MIPS ISA 3 is still in assembly for now. (_CPU_Thread_Idle_body): Rewrote in C. * cpu_asm.S: Rewrote file header. (FRAME,ENDFRAME) now in asm.h. (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C. (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C. (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and leaves other bits in SR alone on task switch. (mips_enable_interrupts,mips_disable_interrupts, mips_enable_global_interrupts,mips_disable_global_interrupts, disable_int, enable_int): Removed. (mips_get_sr): Rewritten as C macro. (_CPU_Thread_Idle_body): Rewritten in C. (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and placed in libcpu. (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved to libcpu/mips/shared/interrupts. (general): Cleaned up comment blocks and #if 0 areas. * idtcpu.h: Made ifdef report an error. * iregdef.h: Removed warning. * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable number defined by libcpu. (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines to access SR. (_CPU_ISR_Set_level): Rewritten as macro for ISA I. (_CPU_Context_Initialize): Honor ISR level in task initialization. (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
* 2000-12-06 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-061-0/+16
| | | | | * rtems/score/cpu.h: When mips ISA level is 1, registers in the context should be 32 not 64 bits.
* 2000-10-24 Alan Cudmore <alanc@linuxstart.com> andJoel Sherrill2000-10-243-58/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | Joel Sherrill <joel@OARcorp.com> * This is a major reworking of the mips64orion port to use gcc predefines as much as possible and a big push to multilib the mips port. The mips64orion port was copied/renamed to mips to be more like other GNU tools. Alan did most of the technical work of determining how to map old macro names used by the mips64orion port to standard compiler macro definitions. Joel did the merge with CVS magic to keep individual file history and did the BSP modifications. Details follow: * Makefile.am: idtmon.h in mips64orion port not present. * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added. * cpu.c: Comments added. * cpu_asm.S: Conditionals changed. MIPS ISA level 1 support added. First attempt at exception/interrupt processing for ISA level 1 and minus any use of IDT/MON added. * idtcpu.h: Conditionals changed to use gcc predefines. * iregdef.h: Ditto. * cpu_asm.h: No real change. Merger required commit. * rtems/Makefile.am: Ditto. * rtems/score/Makefile.am: Ditto. * rtems/score/cpu.h: Change MIPS64ORION to MIPS. * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS. Convert from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
* Port of RTEMS to the Texas Instruments C3x/C4x DSP families includingJoel Sherrill2000-07-261-0/+1
| | | | | | | | | | | a BSP (c4xsim) supporting the simulator included with gdb. This port was done by Joel Sherrill and Jennifer Averett of OAR Corporation. Also included with this port is a space/time optimization to eliminate FP context switch management on CPUs without hardware or software FP. An issue with this port was that sizeof(unsigned32) = sizeof(unsigned8) on this CPU. This required addressing alignment checks and assumptions as well as fixing code that assumed sizeof(unsigned32) == 4.
* Removed no cpu references.Joel Sherrill2000-07-113-3/+3
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* Interrupt stack is allocated in _ISR_Handler_initialization notJoel Sherrill2000-07-031-1/+1
| | | | _Interrupt_Manager_initialization.
* Merged from 4.5.0-beta3aJoel Sherrill2000-06-124-9/+26
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* Patch rtems-rc-4.5.0-13-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>.Joel Sherrill2000-04-132-0/+4
| | | | adds .cvsignore.
* Patch rtems-rc-19991123-rc-2.diff from Ralf CorsepiusJoel Sherrill1999-12-012-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | <corsepiu@faw.uni-ulm.de> which implements automake support for some score/cpu/<RTEMS_CPU> subdirectories and fixes a few minor configuration bugs. To apply: rm -rf c/src/exec/score/cpu/a29k/wrap rm -rf c/src/exec/score/cpu/hppa1.1/wrap rm -rf c/src/exec/score/cpu/i386/wrap rm -rf c/src/exec/score/cpu/mips64orion/wrap rm -rf c/src/exec/score/cpu/no_cpu/wrap patch -p1 < rtems-rc-19991123-rc-2.diff.gz Notes: * I don't see a possiblity to convert the powerpc subdirectory in its current layout to automake the time being. * Besides the fact that this subdirectory is not in single-tree building layout, the actual showstopper is the ifeq $(RTEMS_CPU_MODEL),mpc750) gmake-conditional in powerpc/Makefile.in, which automake (correctly) refuses to handle. * The problem is *not* specific to the powerpc. Other CPUs basically have similar problems (SH:sh7032 vs sh7045, SPARC: erc32.h in score/cpu/sparc), but have been lucky to get around real issues (cf. configuration files below score/cpu/sh/). * From a configuration focused POV this problem boils down to a file/subdirectory selection problem: ppc: 1 or others sh: 1 out of 2 sparc: 1 out of 1 Automake's means to implement such behavior is using conditionals to be evaluated at configuration-time. The old configuration scheme however used make-time conditionals. The SH port was lucky to get around this issue because it applies a selection from a limited set of possible selections, the powerpc however applies a selection from an unlimited set, based on data not being available at configuration time. * Currently I only see two general solutions: 1) make RTEMS_CPU_MODEL available at configuration time, ie. replace make-time configuration by configuration-time configuration 2) Perform the selection at build-time, i.e. always install all files, but use #ifdef #else #endif in source files. This is what the m68k has exploited at other locations inside of the source-tree. => This directory is the last one remaining not using automake below the whole exec/ hierarchy.
* Updated copyright notice.Joel Sherrill1999-11-175-8/+5
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* This is another pass at making sure that nothing outside the BSPJoel Sherrill1999-11-051-0/+9
| | | | | | | | | | | | unnecessarily uses any variables defined by the BSP. On this sweep, use of BSP_Configuration and Cpu_table was eliminated. A significant part of this modification was the addition of macros to access fields in the RTEMS configuration structures. This is necessary to strengthen the division between the BSP independent parts of RTEMS and the BSPs themselves. This started after comments and analysis by Ralf Corsepius <corsepiu@faw.uni-ulm.de>.
* The files in libcpu should not be directly dependent on any BSP. InJoel Sherrill1999-11-041-1/+4
| | | | | | | | | | | particular, using bsp.h, or getting information from the BSP which should properly be obtained from RTEMS is forbidden. This is necessary to strengthen the division between the BSP independent parts of RTEMS and the BSPs themselves. This started after comments and analysis by Ralf Corsepius <corsepiu@faw.uni-ulm.de>. The changes primarily eliminated the need to include bsp.h and peeking at BSP_Configuration. The use of Cpu_table in each BSP needs to be eliminated.
* Patch from Charles-Antoine Gauthier <charles.gauthier@iit.nrc.ca>Joel Sherrill1999-07-291-1/+1
| | | | | to correct a typo CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES was actually typed in as CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
* Moved to proper rtems/scoreJoel Sherrill1999-02-192-0/+148
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* Part of the automake VI patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>:Joel Sherrill1999-02-183-0/+1115
> 4) rtems-rc-19990202-0.diff /reorg-score-cpu.sh > > reorg-score-cpu.sh reorganizes the cpu/<cpu>/* subdirectories in a > similar manner than previous reorg scripts did. rtems-rc-19990202-0.diff > contains the diffs after reorg-score-cpu.sh has been run on a > rtems-19981215 snapshot + my patches up to rtems-rc-19990131-2.diff. > > This patch is rather nasty and may break something. However, I've tested > it for about 10 different target/bsp pairs and believe to have shaken > out most bugs. I wonder about the following .h files that were not moved: a29k/asm.h a29k/cpu_asm.h i386/asm.h i960/asm.h m68k/asm.h m68k/m68302.h m68k/m68360.h m68k/qsm.h m68k/sim.h mips64orion/asm.h mips64orion/cpu_asm.h mips64orion/mips64orion.h no_cpu/asm.h no_cpu/cpu_asm.h powerpc/asm.h powerpc/mpc860.h sh/asm.h sparc/asm.h sparc/erc32.h
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