2000-12-13 Joel Sherrill <joel@OARcorp.com>

	* cpu_asm.h: Removed.
	* Makefile.am: Remove cpu_asm.h.
	* rtems/score/mips64orion.h: Renamed mips.h.
	* rtems/score/mips.h: New file, formerly mips64orion.h.
	Header rewritten.
	(mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
	mips_disable_in_interrupt_mask): New macros.
	* rtems/score/Makefile.am: Reflect renaming mips64orion.h.
	* asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
	few defines that were in <cpu_asm.h>.
	* cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
	MIPS ISA 3 is still in assembly for now.
	(_CPU_Thread_Idle_body): Rewrote in C.
	* cpu_asm.S: Rewrote file header.
	(FRAME,ENDFRAME) now in asm.h.
	(_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
	(_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
	(_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
	leaves other bits in SR alone on task switch.
	(mips_enable_interrupts,mips_disable_interrupts,
	mips_enable_global_interrupts,mips_disable_global_interrupts,
	disable_int, enable_int): Removed.
	(mips_get_sr): Rewritten as C macro.
	(_CPU_Thread_Idle_body): Rewritten in C.
	(init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
	placed in libcpu.
	(exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
	to libcpu/mips/shared/interrupts.
	(general): Cleaned up comment blocks and #if 0 areas.
	* idtcpu.h: Made ifdef report an error.
	* iregdef.h: Removed warning.
	* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
	number defined by libcpu.
	(_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
	to access SR.
	(_CPU_ISR_Set_level): Rewritten as macro for ISA I.
	(_CPU_Context_Initialize): Honor ISR level in task initialization.
	(_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.

4 files changed, 98 insertions, 129 deletions

diff --git a/c/src/exec/score/cpu/mips/rtems/score/Makefile.am b/c/src/exec/score/cpu/mips/rtems/score/Makefile.am
index be1e4fd6b7..097a177601 100644
--- a/c/src/exec/score/cpu/mips/rtems/score/Makefile.am
+++ b/c/src/exec/score/cpu/mips/rtems/score/Makefile.am
@@ -4,7 +4,7 @@
 
 AUTOMAKE_OPTIONS = foreign 1.4
 
-H_FILES = cpu.h mips64orion.h mipstypes.h
+H_FILES = cpu.h mips.h mipstypes.h
 noinst_HEADERS = $(H_FILES)
 
 #
diff --git a/c/src/exec/score/cpu/mips/rtems/score/cpu.h b/c/src/exec/score/cpu/mips/rtems/score/cpu.h
index a12c4369c4..5d5a9a2754 100644
--- a/c/src/exec/score/cpu/mips/rtems/score/cpu.h
+++ b/c/src/exec/score/cpu/mips/rtems/score/cpu.h
@@ -38,17 +38,12 @@
 extern "C" {
 #endif
 
-#include <rtems/score/mips64orion.h>       /* pick up machine definitions */
+#include <rtems/score/mips.h>       /* pick up machine definitions */
 #ifndef ASM
+#include <idtcpu.h>
 #include <rtems/score/mipstypes.h>
 #endif
 
-extern int mips_disable_interrupts( void );
-extern void mips_enable_interrupts( int _level );
-extern int mips_disable_global_interrupts( void );
-extern void mips_enable_global_interrupts( void );
-extern void mips_fatal_error ( int error );
-
 /* conditional compilation parameters */
 
 /*
@@ -530,6 +525,7 @@ SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
  *  by RTEMS.
  */
 
+extern unsigned int mips_interrupt_number_of_vectors;
 #define CPU_INTERRUPT_NUMBER_OF_VECTORS      8
 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
 
@@ -593,10 +589,11 @@ SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
  *  level is returned in _level.
  */
 
-#define _CPU_ISR_Disable( _int_level ) \
-  do{ \
-	_int_level = mips_disable_interrupts(); \
-  }while(0)
+#define _CPU_ISR_Disable( _level ) \
+  do { \
+    mips_get_sr( _level ); \
+    mips_set_sr( (_level) & ~SR_IEC ); \
+  } while(0)
 
 /*
  *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
@@ -605,9 +602,9 @@ SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
  */
 
 #define _CPU_ISR_Enable( _level )  \
-  do{ \
-	mips_enable_interrupts(_level); \
-  }while(0)
+  do { \
+    mips_set_sr(_level); \
+  } while(0)
 
 /*
  *  This temporarily restores the interrupt to _level before immediately
@@ -617,11 +614,11 @@ SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
  */
 
 #define _CPU_ISR_Flash( _xlevel ) \
-  do{ \
-	int _scratch; \
-	_CPU_ISR_Enable( _xlevel ); \
-	_CPU_ISR_Disable( _scratch ); \
-  }while(0)
+  do { \
+    unsigned int _scratch; \
+    _CPU_ISR_Enable( _xlevel ); \
+    _CPU_ISR_Disable( _scratch ); \
+  } while(0)
 
 /*
  *  Map interrupt level in task mode onto the hardware that the CPU
@@ -632,10 +629,30 @@ SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
  *  8 - 255 would be available for bsp/application specific meaning.
  *  This could be used to manage a programmable interrupt controller
  *  via the rtems_task_mode directive.
+ *
+ *  On the MIPS, 0 is all on.  Non-zero is all off.  This only 
+ *  manipulates the IEC.
  */
+
+#if __mips == 3
 extern void _CPU_ISR_Set_level( unsigned32 _new_level );
 
-unsigned32 _CPU_ISR_Get_level( void );
+unsigned32 _CPU_ISR_Get_level( void ); /* in cpu_asm.S */
+#elif __mips == 1
+
+#define _CPU_ISR_Set_level( _new_level ) \
+  do { \
+    unsigned int _sr; \
+    mips_get_sr(_sr); \
+    (_sr) &= ~SR_IEC;                    /* clear the IEC bit */ \
+    if ( !(_new_level) ) (_sr) |= SR_IEC; /* enable interrupts */ \
+    mips_set_sr(_sr); \
+  } while (0)
+
+unsigned32 _CPU_ISR_Get_level( void );  /* in cpu.c */
+#else
+#error "CPU ISR level: unknown MIPS level for SR handling"
+#endif
 
 /* end of ISR handler macros */
 
@@ -670,7 +687,8 @@ unsigned32 _CPU_ISR_Get_level( void );
   	(_the_context)->sp = _stack_tmp; \
   	(_the_context)->fp = _stack_tmp; \
 	(_the_context)->ra = (unsigned64)_entry_point; \
-	(_the_context)->c0_sr = 0; \
+	if (_isr) (_the_context)->c0_sr = 0xff00; \
+	else      (_the_context)->c0_sr = 0xff01; \
   }
 
 /*
@@ -730,11 +748,14 @@ unsigned32 _CPU_ISR_Get_level( void );
  *  halts/stops the CPU.
  */
 
+void mips_fatal_error ( int error );
+
 #define _CPU_Fatal_halt( _error ) \
-  { \
-    mips_disable_global_interrupts(); \
+  do { \
+    unsigned int _level; \
+    _CPU_ISR_Disable(_level); \
     mips_fatal_error(_error); \
-  }
+  } while (0)
 
 /* end of Fatal Error manager macros */
 
@@ -980,15 +1001,6 @@ static inline unsigned int CPU_swap_u32(
 #define CPU_swap_u16( value ) \
   (((value&0xff) << 8) | ((value >> 8)&0xff))
 
-/*
- *  Miscellaneous prototypes 
- *
- *  NOTE:  The names should have mips64orion in them.
- */
-
-void disable_int( unsigned32 mask );
-void enable_int( unsigned32 mask );
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/c/src/exec/score/cpu/mips/rtems/score/mips.h b/c/src/exec/score/cpu/mips/rtems/score/mips.h
index 90e959bd47..1f2740c49d 100644
--- a/c/src/exec/score/cpu/mips/rtems/score/mips.h
+++ b/c/src/exec/score/cpu/mips/rtems/score/mips.h
@@ -1,23 +1,6 @@
-/*  mips64orion.h
+/*  mips.h
  *
- *  Author:     Craig Lebakken <craigl@transition.com>
- *
- *  COPYRIGHT (c) 1996 by Transition Networks Inc.
- *
- *  To anyone who acknowledges that this file is provided "AS IS"
- *  without any express or implied warranty:
- *      permission to use, copy, modify, and distribute this file
- *      for any purpose is hereby granted without fee, provided that
- *      the above copyright notice and this notice appears in all
- *      copies, and that the name of Transition Networks not be used in
- *      advertising or publicity pertaining to distribution of the
- *      software without specific, written prior permission.
- *      Transition Networks makes no representations about the suitability
- *      of this software for any purpose.
- *
- *  Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h:
- *
- *  COPYRIGHT (c) 1989-1999.
+ *  COPYRIGHT (c) 1989-2000.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -68,6 +51,56 @@ extern "C" {
 
 #define CPU_NAME "MIPS"
 
+/*
+ *  Some macros to access registers
+ */
+
+#define mips_get_sr( _x ) \
+  do { \
+    asm volatile( "mfc0 %0, $12; nop" : "=g" (_x) :  ); \
+  } while (0)
+
+#define mips_set_sr( _x ) \
+  do { \
+    unsigned int __x = (_x); \
+    asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \
+  } while (0)
+
+/*
+ *  Manipulate interrupt mask 
+ *
+ *  mips_unmask_interrupt( _mask) 
+ *    enables interrupts - mask is positioned so it only needs to be or'ed
+ *    into the status reg. This also does some other things !!!! Caution
+ *    should be used if invoking this while in the middle of a debugging
+ *    session where the client may have nested interrupts.
+ *
+ *  mips_mask_interrupt( _mask )
+ *    disable the interrupt - mask is the complement of the bits to be
+ *    cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff
+ *
+ *
+ *  NOTE: mips_mask_interrupt() used to be disable_int().
+ *        mips_unmask_interrupt() used to be enable_int().
+ *
+ */
+
+#define mips_enable_in_interrupt_mask( _mask ) \
+  do { \
+    unsigned int _sr; \
+    mips_get_sr( _sr ); \
+    _sr |= (_mask) | SR_IEC; \
+    mips_set_sr( _sr ); \
+  } while (0)
+
+#define mips_disable_in_interrupt_mask( _mask ) \
+  do { \
+    unsigned int _sr; \
+    mips_get_sr( _sr ); \
+    _sr &= ~(_mask); \
+    mips_set_sr( _sr ); \
+  } while (0)
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/c/src/exec/score/cpu/mips/rtems/score/mips64orion.h b/c/src/exec/score/cpu/mips/rtems/score/mips64orion.h
deleted file mode 100644
index 90e959bd47..0000000000
--- a/c/src/exec/score/cpu/mips/rtems/score/mips64orion.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*  mips64orion.h
- *
- *  Author:     Craig Lebakken <craigl@transition.com>
- *
- *  COPYRIGHT (c) 1996 by Transition Networks Inc.
- *
- *  To anyone who acknowledges that this file is provided "AS IS"
- *  without any express or implied warranty:
- *      permission to use, copy, modify, and distribute this file
- *      for any purpose is hereby granted without fee, provided that
- *      the above copyright notice and this notice appears in all
- *      copies, and that the name of Transition Networks not be used in
- *      advertising or publicity pertaining to distribution of the
- *      software without specific, written prior permission.
- *      Transition Networks makes no representations about the suitability
- *      of this software for any purpose.
- *
- *  Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h:
- *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.OARcorp.com/rtems/license.html.
- *
- *  $Id$
- */
-/* @(#)mips64orion.h       08/29/96     1.3 */
-
-#ifndef _INCLUDE_MIPS_h
-#define _INCLUDE_MIPS_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- *  This file contains the information required to build
- *  RTEMS for a particular member of the "no cpu"
- *  family when executing in protected mode.  It does
- *  this by setting variables to indicate which implementation
- *  dependent features are present in a particular member
- *  of the family.
- */
- 
-#if defined(__mips_soft_float)
-#define MIPS_HAS_FPU 0
-#else
-#define MIPS_HAS_FPU 1
-#endif 
-
-#if (__mips == 1)
-#define CPU_MODEL_NAME  "ISA Level 1 or 2"
-#elif (__mips == 3)
-#if defined(__mips64)
-#define CPU_MODEL_NAME  "ISA Level 4"
-#else
-#define CPU_MODEL_NAME  "ISA Level 3"
-#endif
-#else
-#error "Unknown MIPS ISA level"
-#endif
-
-/*
- *  Define the name of the CPU family.
- */
-
-#define CPU_NAME "MIPS"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ! _INCLUDE_MIPS_h */
-/* end of include file */