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21 hoursbsp/aarch64: Add new Raspberry Pi 4B BSPHEADmasterMohd Noor Aman8-0/+957
This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently only LP64 ABI is supported. ILP32 is not supported. RAM starts from 0x80000 in 64Bit kernel mode and MMU from 0x0. All Raspberrypi Pi 4B models and Raspberry Pi 400 are supported. All the IRQs are similiar to the older Raspberry pi 2 ARM BSP. Raspberry Pi 4B has 2 types of UARTs. Only PL011 serial is supported currently. Mini-UART is not supported. Mini-UART is default UART on the board so it needs to be disabled by adding "dtoverlay=disable-bt" to the config.txt. No support for additional 4 PL011-UARTs on the board. The raspberrypi.h includes many of the address required for the future development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.
13 daysbsps: Fix format specifierSebastian Huber1-1/+1
Close #4722.
14 daysbsps/arm: Mark functions in start.SSebastian Huber1-0/+2
Add the function type to _start() and bsp_start_hook_0_done() so that the linker can generate ARM/Thumb interworking code. Update #4202.
14 daysbsps/arm: Move bsp_start_hook_0_done()Sebastian Huber2-2/+6
Declare bsp_start_hook_0_done() in <bsp/start.h>.
14 daysbsps/arm: Add comment about banked FIQ registersSebastian Huber1-0/+1
2022-09-20bsps/shared/: Use device tree blobPadmarao Begari1-0/+8
If the bsp is integrated and supported a device tree blob(dtb) then use dtb instead of using it from the U-Boot (BSP_START_COPY_FDT_FROM_U_BOOT=False).
2022-09-20bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari8-4/+132
The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
2022-09-20bsps/riscv: Add device tree blobPadmarao Begari2-0/+967
Add the basic Microchip PolarFire SoC device tree source and blob The mpfs-dtb.h is generated by the bin2hex https://github.com/padmaraob/bin2hex 1.Compile and build the bin2hex.c $ gcc -o bin2hex bin2hex.c 2.Generate the mpfs.dtb from the mpfs.dts $ dtc -O dtb -o mpfs.dtb mpfs.dts 3.Generate the mpfs-dtb.h Header file from the mpfs.dtb. $ ./bin2hex mpfs.dtb
2022-09-20bsp/tms570: Fix declarationsSebastian Huber1-4/+4
This avoids multiple definition errors.
2022-09-19bsps/riscv/riscv: Fix fe310_uart_readAlan Cudmore1-2/+5
Note: Resending after learning how to use git send-email, please disregard previous message. This fixes the riscv fe310 console driver fe310_uart_read function. The function reads the RX status/data register to check if data is available, but discards the data and reads it a seconds time. Also cleared the interrupt enable bit in the first_open function. Close #4719
2022-09-19Do not use RTEMS_INLINE_ROUTINESebastian Huber12-56/+56
Directly use "static inline" which is available in C99 and later. This brings the RTEMS implementation closer to standard C. Close #3935.
2022-09-08powerpc: Add support for VRSAVESebastian Huber2-8/+337
The VRSAVE feature of the Altivec unit can be used to reduce the amount of Altivec registers which need to be saved/restored during interrupt processing and context switches. In order to use the VRSAVE optimization a corresponding multilib (-mvrsave) is required, see GCC configuration. The -mvrsave option must be added to the ABI_FLAGS of the BSP. Currently only the -mcpu=e6500 based QorIQ BSP support this optimization. Update #4712.
2022-09-06bsp/riscv: Add NOEL-V BSPMartin Aberg9-0/+472
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the following NOEL-V FPGA example design ranges available from Cobham Gaisler. Follow the links for free bit-streams, DTS/DTB, user's manuals and quick-start guides: - NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7) - NOEL-PF-EX (https://www.gaisler.com/NOEL-PF) - NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU) Uses the shared GRLIB APBUART console driver "apbuart_termios.c". APBUART devices are probed using device tree. Closes #4225.
2022-09-06bsp/riscv: Work area size based on /memory node in fdtDaniel Cederman1-0/+144
Uses the first entry in the /memory node to determine the end of the work area. Falls back on linker symbol if unable to parse the node.
2022-08-25bsps/xilinx/versal: Add Cadence I2C driver supportChris Johns4-0/+82
2022-08-23bsps/amd64: remove -Werror from ABI flagsStephen Clark1-1/+0
The ABI flags for the amd64 BSP contain the -Werror=return-type flag. There is no reason for this to be there so it has been removed. The same option has also been removed amd64.cfg file.
2022-08-12bsps: Fix .data.rel.ro placementSebastian Huber7-7/+7
The .data.rel.ro* linker input section pattern accidentally matches with writeable data those symbol name starts with "ro". Close #4701.
2022-07-28aarch64/versal: Support DDRMC0 region 0 and 1Chris Johns3-0/+59
- Support DDRMC0 region 0 up to 2G in size - Support DDRMC0 region 1 with DDR memory greater than 2G up to the DDRMC0 max amount - Extend the heap with region 1's memory Closes #4684
2022-07-28basp/aarch64: Make the unexpected sections origin address 64bitChris Johns1-1/+1
Update #4684
2022-07-27Use __asm__ for standard C compatibilitySebastian Huber3-24/+24
2022-07-21aarch64: Use page table level 0Kinsey Moore3-15/+58
This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports.
2022-07-18aarch64: Memory map the noinit sectionKinsey Moore2-0/+8
This section was added recently and must be mapped to be accessed without generating an exception.
2022-07-15bsps: Sort .noinit* sectionsSebastian Huber56-56/+56
Sort the .noinit* input sections by name first, then by alignment if two sections have the same name. This allows the placement of begin/end symbols to initialize some areas with a special value. Update #4678.
2022-07-12bsps/v850/gdbv850sim: Change license to BSD-2Joel Sherrill3-9/+66
Updates #3053.
2022-07-12bsps/sparc64/usiii: Change license to BSD-2Joel Sherrill2-6/+44
Updates #3053.
2022-07-12bsps/sparc64/shared: Change license to BSD-2Joel Sherrill3-9/+66
Updates #3053.
2022-07-12bsps/sparc64/niagara: Change license to BSD-2Joel Sherrill3-9/+66
Updates #3053.
2022-07-12bsps/sparc64/include: Change license to BSD-2Joel Sherrill2-6/+44
Updates #3053.
2022-07-12bsps/sh/shsim: Change license to BSD-2Joel Sherrill4-12/+88
Updates #3053.
2022-07-12bsps/sh/shared: Change license to BSD-2Joel Sherrill1-3/+22
Updates #3053.
2022-07-12bsps/sh/gensh2: Change license to BSD-2Joel Sherrill4-12/+88
Updates #3053.
2022-07-12bsps/sh/gensh1: Change license to BSD-2Joel Sherrill1-3/+22
Updates #3053.
2022-07-12bsps/powerpc/virtex5: Change license to BSD-2Joel Sherrill2-6/+44
Updates #3053.
2022-07-12bsps/powerpc/virtex4: Change license to BSD-2Joel Sherrill2-6/+44
Updates #3053.
2022-07-12bsps/powerpc/virtex: Change license to BSD-2Joel Sherrill2-6/+44
Updates #3053.
2022-07-12bsps/powerpc/tqm8xx: Change license to BSD-2Joel Sherrill7-21/+154
Updates #3053.
2022-07-12bsps/powerpc/t32mppc: Change license to BSD-2Joel Sherrill8-24/+176
Updates #3053.
2022-07-12bsps/powerpc/shared: Change license to BSD-2Joel Sherrill18-54/+396
Updates #3053.
2022-07-12bsps/powerpc/qoriq: Change license to BSD-2Joel Sherrill31-93/+682
Updates #3053.
2022-07-12bsps/powerpc/qemuppc: Change license to BSD-2Joel Sherrill4-12/+88
Updates #3053.
2022-07-12bsps/powerpc/psim: Change license to BSD-2Joel Sherrill7-21/+154
Updates #3053.
2022-07-12bsps/powerpc/mpc8260ads: Change license to BSD-2Joel Sherrill2-6/+44
Updates #3053.
2022-07-12bsps/powerpc/mpc55xxevb: Change license to BSD-2Joel Sherrill48-144/+1056
Updates #3053.
2022-07-12bsps/powerpc/include: Change license to BSD-2Joel Sherrill8-24/+176
Updates #3053.
2022-07-12bsps/powerpc/83xx: Change license to BSD-2Joel Sherrill18-54/+396
Updates #3053.
2022-07-12bsps/powerpc/gen5200: Change license to BSD-2Joel Sherrill21-63/+462
Updates #3053.
2022-07-12bsps/powerpc/beatnik: Change license to BSD-2Joel Sherrill1-3/+22
Updates #3053.
2022-07-12bsps/no_cpu/no_bsp: Change license to BSD-2Joel Sherrill12-36/+264
Updates #3053.
2022-07-12bsps/nios2/nios2_iss: Change license to BSD-2Joel Sherrill1-3/+22
Updates #3053.
2022-07-12bsps/moxie/moxiesim: Change license to BSD-2Joel Sherrill1-3/+22
Updates #3053.