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* bsps/riscv: Fix PLIC enable register countSebastian Huber2022-11-101-2/+2
| | | | Each PLIC enable register has 32 bits, so we have to divide by 32.
* bsps/riscv: Skip init on not configured processorsSebastian Huber2022-11-101-0/+11
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* bsps/riscv: Simplify riscv_plic_init()Sebastian Huber2022-11-101-30/+39
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* bsps/riscv: Simplify riscv_clint_init()Sebastian Huber2022-11-101-14/+25
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* bsps/riscv: Add tm27 supportSebastian Huber2022-11-101-1/+136
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* bsps/riscv: Always dispatch software interruptsSebastian Huber2022-11-101-3/+2
| | | | This helps to run the interrupt API validation tests.
* bsps/riscv: bsp_interrupt_get/set_affinity()Sebastian Huber2022-11-102-14/+7
| | | | | Provide bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if RTEMS_SMP is enabled. Replace fatal error with a status code.
* bsps/riscv: bsp_interrupt_raise_on()Sebastian Huber2022-11-101-4/+20
| | | | Implement bsp_interrupt_raise_on() and bsp_interrupt_raise().
* bsps/riscv: bsp_interrupt_is_pending()Sebastian Huber2022-11-101-2/+25
| | | | Implement this function.
* bsps/riscv: bsp_interrupt_get_attributes()Sebastian Huber2022-11-101-0/+15
| | | | Implement this function.
* bsps/riscv: Improve bsp_interrupt_vector_disable()Sebastian Huber2022-11-101-0/+8
| | | | Add support for hart-specific software and timer interrupts.
* bsps/riscv: Improve bsp_interrupt_vector_enable()Sebastian Huber2022-11-101-0/+8
| | | | Add support for hart-specific software and timer interrupts.
* bsps/riscv: bsp_interrupt_vector_is_enabled()Sebastian Huber2022-11-101-2/+47
| | | | Implement this function.
* bsps/riscv: bsp_interrupt_is_valid_vector()Sebastian Huber2022-11-102-1/+18
| | | | Implement this function.
* config: Place init task storage area in .rtemsstackSebastian Huber2022-11-092-12/+12
| | | | | This avoids a superfluous zero initialization of the task storage area. This reduces the system initialization time.
* bsps/aarch64: Ensure FPU trap state is consistentKinsey Moore2022-11-091-0/+6
| | | | | RTEMS may be booted from a dirty environment. Ensure that FPU trap settings are consistent.
* zynqmp: Add support for the CFC-400XKinsey Moore2022-11-098-1/+657
| | | | | | | | This adds a BSP variant for the ZynqMP BSP family to support the Innoflight CFC-400X platform. To properly support the CFC-400X, device trees were added to the ZynqMP platform due to both the optional management interface as well as alternate physical configuration of the ethernet interfaces.
* bsps/riscv: Use start data for objectSebastian Huber2022-11-041-0/+6
| | | | | | Maybe this helps to ensure that the object is properly aligned. Update #4658.
* bsps/arm/beagle/dcan: Added DCAN supportPrashanth S2022-10-307-0/+11552
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* bsps/riscv: Workaround for sporadic linker issuesSebastian Huber2022-10-281-0/+1
| | | | | | | | | | | Disable the linker relaxation in start.S to work around an issue described here: https://mail.gnu.org/archive/html/bug-binutils/2021-03/msg00164.html The real issue is probably in the linker command file or the linker itself. Update #4658.
* bsps/arm: fix Cortex-M7 systick reload valueDariusz Sabala2022-10-261-1/+1
| | | | | | | | | | | | - see ARM DUI 0646C Arm Cortex-M7 Devices Generic User Guide "The RELOAD value is calculated according to its use. For example, to generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. If the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99." - see routines used in CMSIS project for reference Close #4746.
* bsps: Add Cache Manager implementation groupSebastian Huber2022-10-241-4/+39
| | | | Update #3707.
* bsps: Improve riscv console FDT parsingAlan Cudmore2022-10-141-9/+5
| | | | | | | | | | This fixes a problem with parsing the FDT compatible property by replacing the RISCV_CONSOLE_IS_COMPATIBLE macro with calls to the fdt_stringlist_contains function. The macro only works when the compatible FDT entry is a single string and not a list of strings. The new call will compare each item in the string list. Close #4728.
* riscv: Move functions to avoid build issuesSebastian Huber2022-10-141-10/+0
| | | | | The _RISCV_Map_cpu_index_to_hardid() and _RISCV_Map_hardid_to_cpu_index() functions must be available to all riscv BSPs.
* score: Add CPU_THREAD_LOCAL_STORAGE_VARIANTSebastian Huber2022-10-141-1/+1
| | | | Update #3835.
* bsp/aarch64: Add new Raspberry Pi 4B BSPMohd Noor Aman2022-10-048-0/+957
| | | | | | | | | | | | | | | | | This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently only LP64 ABI is supported. ILP32 is not supported. RAM starts from 0x80000 in 64Bit kernel mode and MMU from 0x0. All Raspberrypi Pi 4B models and Raspberry Pi 400 are supported. All the IRQs are similiar to the older Raspberry pi 2 ARM BSP. Raspberry Pi 4B has 2 types of UARTs. Only PL011 serial is supported currently. Mini-UART is not supported. Mini-UART is default UART on the board so it needs to be disabled by adding "dtoverlay=disable-bt" to the config.txt. No support for additional 4 PL011-UARTs on the board. The raspberrypi.h includes many of the address required for the future development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.
* bsps: Fix format specifierSebastian Huber2022-09-231-1/+1
| | | | Close #4722.
* bsps/arm: Mark functions in start.SSebastian Huber2022-09-221-0/+2
| | | | | | | Add the function type to _start() and bsp_start_hook_0_done() so that the linker can generate ARM/Thumb interworking code. Update #4202.
* bsps/arm: Move bsp_start_hook_0_done()Sebastian Huber2022-09-222-2/+6
| | | | Declare bsp_start_hook_0_done() in <bsp/start.h>.
* bsps/arm: Add comment about banked FIQ registersSebastian Huber2022-09-221-0/+1
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* bsps/shared/: Use device tree blobPadmarao Begari2022-09-201-0/+8
| | | | | | If the bsp is integrated and supported a device tree blob(dtb) then use dtb instead of using it from the U-Boot (BSP_START_COPY_FDT_FROM_U_BOOT=False).
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-208-4/+132
| | | | | | | | The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
* bsps/riscv: Add device tree blobPadmarao Begari2022-09-202-0/+967
| | | | | | | | | | | | | | | | | Add the basic Microchip PolarFire SoC device tree source and blob The mpfs-dtb.h is generated by the bin2hex https://github.com/padmaraob/bin2hex 1.Compile and build the bin2hex.c $ gcc -o bin2hex bin2hex.c 2.Generate the mpfs.dtb from the mpfs.dts $ dtc -O dtb -o mpfs.dtb mpfs.dts 3.Generate the mpfs-dtb.h Header file from the mpfs.dtb. $ ./bin2hex mpfs.dtb
* bsp/tms570: Fix declarationsSebastian Huber2022-09-201-4/+4
| | | | This avoids multiple definition errors.
* bsps/riscv/riscv: Fix fe310_uart_readAlan Cudmore2022-09-191-2/+5
| | | | | | | | | | | Note: Resending after learning how to use git send-email, please disregard previous message. This fixes the riscv fe310 console driver fe310_uart_read function. The function reads the RX status/data register to check if data is available, but discards the data and reads it a seconds time. Also cleared the interrupt enable bit in the first_open function. Close #4719
* Do not use RTEMS_INLINE_ROUTINESebastian Huber2022-09-1912-56/+56
| | | | | | | Directly use "static inline" which is available in C99 and later. This brings the RTEMS implementation closer to standard C. Close #3935.
* powerpc: Add support for VRSAVESebastian Huber2022-09-082-8/+337
| | | | | | | | | | | | | | The VRSAVE feature of the Altivec unit can be used to reduce the amount of Altivec registers which need to be saved/restored during interrupt processing and context switches. In order to use the VRSAVE optimization a corresponding multilib (-mvrsave) is required, see GCC configuration. The -mvrsave option must be added to the ABI_FLAGS of the BSP. Currently only the -mcpu=e6500 based QorIQ BSP support this optimization. Update #4712.
* bsp/riscv: Add NOEL-V BSPMartin Aberg2022-09-069-0/+472
| | | | | | | | | | | | | | | | | | | | Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the following NOEL-V FPGA example design ranges available from Cobham Gaisler. Follow the links for free bit-streams, DTS/DTB, user's manuals and quick-start guides: - NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7) - NOEL-PF-EX (https://www.gaisler.com/NOEL-PF) - NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU) Uses the shared GRLIB APBUART console driver "apbuart_termios.c". APBUART devices are probed using device tree. Closes #4225.
* bsp/riscv: Work area size based on /memory node in fdtDaniel Cederman2022-09-061-0/+144
| | | | | Uses the first entry in the /memory node to determine the end of the work area. Falls back on linker symbol if unable to parse the node.
* bsps/xilinx/versal: Add Cadence I2C driver supportChris Johns2022-08-254-0/+82
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* bsps/amd64: remove -Werror from ABI flagsStephen Clark2022-08-231-1/+0
| | | | The ABI flags for the amd64 BSP contain the -Werror=return-type flag. There is no reason for this to be there so it has been removed. The same option has also been removed amd64.cfg file.
* bsps: Fix .data.rel.ro placementSebastian Huber2022-08-127-7/+7
| | | | | | | The .data.rel.ro* linker input section pattern accidentally matches with writeable data those symbol name starts with "ro". Close #4701.
* aarch64/versal: Support DDRMC0 region 0 and 1Chris Johns2022-07-283-0/+59
| | | | | | | | | | | - Support DDRMC0 region 0 up to 2G in size - Support DDRMC0 region 1 with DDR memory greater than 2G up to the DDRMC0 max amount - Extend the heap with region 1's memory Closes #4684
* basp/aarch64: Make the unexpected sections origin address 64bitChris Johns2022-07-281-1/+1
| | | | Update #4684
* Use __asm__ for standard C compatibilitySebastian Huber2022-07-273-24/+24
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* aarch64: Use page table level 0Kinsey Moore2022-07-213-15/+58
| | | | | | | | | This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports.
* aarch64: Memory map the noinit sectionKinsey Moore2022-07-182-0/+8
| | | | | This section was added recently and must be mapped to be accessed without generating an exception.
* bsps: Sort .noinit* sectionsSebastian Huber2022-07-1556-56/+56
| | | | | | | | Sort the .noinit* input sections by name first, then by alignment if two sections have the same name. This allows the placement of begin/end symbols to initialize some areas with a special value. Update #4678.
* bsps/v850/gdbv850sim: Change license to BSD-2Joel Sherrill2022-07-123-9/+66
| | | | Updates #3053.
* bsps/sparc64/usiii: Change license to BSD-2Joel Sherrill2022-07-122-6/+44
| | | | Updates #3053.
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