summaryrefslogtreecommitdiffstats
path: root/bsps (follow)
Commit message (Collapse)AuthorAgeFilesLines
* bsps/xilinx-zynqmp: Add JFFS2 GQSPI NOR driverAlex White2023-01-273-0/+249
|
* bsps: Add Xilinx GQSPI flash helperAlex White2023-01-272-0/+2086
| | | | | | This adds helper functions for working with NOR flash connected to the Xilinx GQSPI controller. The helper functions are based on Xilinx's QSPIPSU flash interrupt example.
* bsps: Import Xilinx GQSPI driverAlex White2023-01-279-0/+4689
| | | | | | | | This adds Xilinx's driver for the Xilinx GQSPI controller embedded in the ZynqMP SoC. Within that device alone, it is possible to access this peripheral from MicroBlaze, ARMv7, and ARMv8 cores. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/dev/spi/VERSION.
* intr: Add Interrupt Manager implementation groupSebastian Huber2023-01-2435-59/+59
| | | | | | | The shared BSP interrupt controller support code actually implements parts of the Interrupt Manager. Update #3706.
* clockdrv: Add clock driver implementation groupSebastian Huber2023-01-244-20/+22
| | | | | | Use standard wording in Clock Driver related files. Update #3706.
* tm27: Avoid function pointer castsSebastian Huber2023-01-2434-41/+75
| | | | | | | Add TM27_USE_VECTOR_HANDLER to select the interrupt handler type used by the <tm27.h> implementation. Close #4820.
* bsp/tms570: Fix define redefinition errorSebastian Huber2023-01-171-2/+2
|
* riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORTSebastian Huber2023-01-126-12/+30
| | | | | | | | Low-end configurations may want to have the HTIF support removed. Enable the option by default. Fix formatting. Fix node validity checks. Updates #4779.
* bsps/xil: Use the LP64 header for ILP32Kinsey Moore2023-01-041-10/+25
| | | | | | | Xilinx's upstream ILP32 xil_cache.h header is out of date and broken. This provides a copy of the LP64 header in place of the ILP32 header since the LP64 header includes all the correct types to work with either data model.
* bsps: Move ZynqMP-specific info into the BSPKinsey Moore2023-01-043-117/+2
| | | | | | The address of the nandpsu peripheral is specific to the ZynqMP SoC and not relevant to other devices that might have one or more instances of this peripheral.
* bsp/qoriq: Add qoriq_mmu_adjust_and_write_to_tlb1()Sebastian Huber2023-01-033-7/+38
|
* bsp/qoriq: Add qoriq_mmu_find_free_tlb1_entry()Sebastian Huber2023-01-032-1/+27
|
* bsp/qoriq: Support message signaled interruptsSebastian Huber2023-01-032-17/+244
|
* bsp/qoriq: Clear shared message signaled interruptsSebastian Huber2023-01-031-0/+5
|
* bsp/qoriq: Use only pic_is_ipi()Sebastian Huber2023-01-031-11/+6
|
* bsps: Import Xilinx NAND driverKinsey Moore2022-12-2310-0/+5622
| | | | | | | | | | This adds Xilinx's driver for the Xilinx NAND controller embedded in the ZynqMP SoC. Within that device alone, it is possible to access this peripheral from MicroBlaze, ARMv7, and ARMv8 cores. This has been added to the hardware ZynqMP BSPs since QEMU does not support emulation of this peripheral. This driver supports polled operation only. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/dev/nand/VERSION.
* bsps: Import Xilinx support codeKinsey Moore2022-12-2330-0/+5366
| | | | | | | | | This support code is necessary for many Xilinx-provided bare metal device drivers supported on ARM, AArch64, and MicroBlaze platforms. Support for all of these architectures is kept under bsps/include due to multiple architecture variants being supported which requires complex logic in the build system. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/xil/VERSION.
* RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORTHesham Almatary2022-12-236-26/+18
| | | | Updates #4779
* bsp/atsam: Allow to use custom SDRAMChristian Mauderer2022-12-151-0/+7
| | | | | | | | | | | With the old build system in RTEMS 5 that was possible by just overwriting BOARD_Sdram_Config and setting a custom ATSAM_MEMORY_SDRAM_SIZE during building the BSP. In the new build system that ATSAM_MEMORY_SDRAM_SIZE is set exclusively by the selected SDRAM chip. This patch adds the possibility to specify a "custom-0x100000" or similar as SDRAM type where the number gives the SDRAM size.
* bsps/atsam: Add NULL pointer protectionChristian Mauderer2022-12-155-2/+28
|
* bsps/atsam: Fix unidirectional SPI transfersChristian Mauderer2022-12-151-57/+131
| | | | | | | | | A SPI transfer where the Rx or Tx buffer is set to NULL currently transfers or overwrites data starting from address 0x00000000 via DMA. This patch changes the DMA setup so that dummy transfers are done. Just reading / writing to a single location is simpler than changing the whole logic of the transfer depending on the passed buffers.
* bsps/zynqmp: Fix and update device treesKinsey Moore2022-12-074-115/+137
| | | | | | | | Add ref-clock-num identifiers to the device tree to ensure that interfaces use the correct clocks even when some are not used due to unconnected MII busses. This also adjusts the default ZynqMP PHY attachment to RGMII-ID which was the default before device trees were introduced.
* config: Add CONFIGURE_RECORD_INTERRUPTS_ENABLEDSebastian Huber2022-12-021-0/+97
| | | | | | | | This enables the tracing of interrupt entry/exit events through an application configuration option. The interrupt processing can be viewed with Trace Compass using rtems-record-lttng from the RTEMS Tools. Update #4769.
* bsps/irq: Add bsp_interrupt_get_dispatch_table_slot()Sebastian Huber2022-12-024-8/+26
| | | | Update #4769.
* bsps/irq: Rename handler in dispatch tableSebastian Huber2022-12-026-59/+57
| | | | | | | The name handler table was a bit misleading after the last rework. Rename it to distach table. Update the documentation accordingly. Update #4769.
* bsps/microblaze: Fix console interrupt build errorsAlex White2022-11-293-1/+21
| | | | | | This fixes build errors seen when building with console interrupts enabled. A few places were missing bspopts.h includes, and one of the UART functions was not defined.
* bsps/riscv: Simplify PLIC supportSebastian Huber2022-11-231-28/+30
| | | | | In uniprocessor configurations there is no need to take interrupt affinities into account for the interrupt vector enable/disable.
* bsps/riscv: Fix PLIC enable register countSebastian Huber2022-11-231-3/+5
|
* bsps/riscv: Add riscv_plic_cpu_0_init()Sebastian Huber2022-11-231-13/+23
| | | | Move boot processor initialization of PLIC to separate function.
* bsps/riscv: Fix bsp_fdt_map_intr()Sebastian Huber2022-11-231-1/+1
| | | | | The interrupt numbers in the device tree are usually PLIC interrupts. Map the number to the vector number associated with an external interrupt.
* aarch64/versal: Add UART interrupt supportChris Johns2022-11-224-39/+324
|
* rtems/versal: Updated mmu to include mapping for SDHCI devices on versalAaron Nyholm2022-11-221-1/+5
| | | | | | Tested on VCK190 Updates #4762
* bsps/zynqmp: Use direct fdt_* callsKinsey Moore2022-11-181-22/+10
| | | | | | This changes the ZynqMP device tree parsing over to direct libfdt calls to avoid inclusion of malloc() in the base BSP which currently causes sp01 to fail due to unexpected use of TLS space.
* aarch64/mmu: Prevent block descriptors at level -1Kinsey Moore2022-11-171-10/+13
| | | | | | | | | In the original implementation, level -1 was unused and all levels could have block-like descriptors (level 2 block descriptors are called page descriptors). When support for level -1 page tables was added the constraint on level -1 block descriptors was not honored. This prevents block descriptors from being mapped at level -1 since the hardware will not map them properly.
* bsps/riscv: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman2022-11-145-12/+90
| | | | | | | | | This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053.
* bsps/sparc: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman2022-11-1440-132/+894
| | | | | | | | | This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053.
* bsps/shared/grlib: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman2022-11-1467-199/+1453
| | | | | | | | | This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053.
* bsps/include/grlib: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman2022-11-1459-168/+1319
| | | | | | | | | This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053.
* bsps/include/libchip: Remove legacy networking header fileDaniel Cederman2022-11-141-152/+0
|
* bsps/riscv: Fix software interrupt dispatchingSebastian Huber2022-11-112-2/+33
| | | | | | | In SMP configurations, there may be no software interrupt handler installed when the software interrupt is processed. Add the new interrupt handler dispatch variant bsp_interrupt_handler_dispatch_unlikely() for this special case.
* bsps/noel: Fix interrupt supportSebastian Huber2022-11-111-0/+2
|
* bsps/riscv: Fix PLIC enable register countSebastian Huber2022-11-101-2/+2
| | | | Each PLIC enable register has 32 bits, so we have to divide by 32.
* bsps/riscv: Skip init on not configured processorsSebastian Huber2022-11-101-0/+11
|
* bsps/riscv: Simplify riscv_plic_init()Sebastian Huber2022-11-101-30/+39
|
* bsps/riscv: Simplify riscv_clint_init()Sebastian Huber2022-11-101-14/+25
|
* bsps/riscv: Add tm27 supportSebastian Huber2022-11-101-1/+136
|
* bsps/riscv: Always dispatch software interruptsSebastian Huber2022-11-101-3/+2
| | | | This helps to run the interrupt API validation tests.
* bsps/riscv: bsp_interrupt_get/set_affinity()Sebastian Huber2022-11-102-14/+7
| | | | | Provide bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if RTEMS_SMP is enabled. Replace fatal error with a status code.
* bsps/riscv: bsp_interrupt_raise_on()Sebastian Huber2022-11-101-4/+20
| | | | Implement bsp_interrupt_raise_on() and bsp_interrupt_raise().
* bsps/riscv: bsp_interrupt_is_pending()Sebastian Huber2022-11-101-2/+25
| | | | Implement this function.
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-20 20:58:31 +0000