| Commit message (Collapse) | Author | Age | Files | Lines |
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- Fixes timeout for smpipi01 where:
+ Main thread sends perform jobs to worker cpu while it is already
performing jobs
+ Interrupt on worker cpu performs jobs, but with empty job list
+ Worker cpu continues to execut previous job and adds new job list
to itself, which is never performed, since the interrupt has already
been handled
+ Main thread blocks forever on barrier D
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- Do not forward Clock_isr through Clock_driver_support_at_tick as this
will cause every processor to send IPIs with Clock_isr therby creating
an infinie loop
- Instead the processor handling the clock interrupt causes all other
processors to call rtems_timecounter_tick to update their tick count
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- Defines CPU_Interrupt_frame in cpu_impl.h
- Updates isq_asm.S to save/restore registers in matching order to
interrupt frame
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Create a GS segment in the GDT for each processor for storing TLS.
This makes the GDT in startAP.S obsolete as all processors now share the
same GDT, which is passed to each AP at startup.
The correct segment for each processor is calculated in cpu_asm.S.
Update #3335
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start16.S is now only used for SMP configurations to start the
application processors.
This commit removes all unnecessary parts for this job,
i.e. video conssole initalisation, A20 gate activation
and all non-AP related code.
Update #3335
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Updates #2962
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Updates #2962
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Updates #2962
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Updates #2962
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Update #3970.
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_CPU_Counter_frequency() can be called by the rtems_counter
initialization before arm_gt_clock_initialize() initializes the value
used in _CPU_Counter_frequency().
Closes #3961.
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Some imx chips or boards don't use the same frequency for ECSPI and IPG.
Update #3869
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1) _Memory_Initialize makes pointer from integer
without a cast.
2) printf format error, expects %u but %lu provided.
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Updates #3938.
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Updates #3938.
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Updates #3938.
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Updates #3938.
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Updates #3938.
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Updates #3938.
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Update #3938.
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Closes #3936.
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Fixes #3903
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CLOCK_DRIVER_ISRS_PER_TICK is the configuration define,
CLOCK_DRIVER_ISRS_PER_TICK_VALUE is the actual value of ISRS per clock
tick, therefore use this one to reset the Clock_driver_isrs after each
tick.
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Statically initialize the ARMv7-M vector table to allow a placement in
ROM with read-only MPU settings.
Change licence to BSD-2-Clause in some files.
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Close #3921.
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Closes #3611.
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This fixes linker issues on the powerpc/virtex4 and powerpc/virtex5
BSPs.
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Add a simplified path evaluation function IMFS_eval_path_devfs() for a
device only IMFS configuration.
The code size can be further reduced by the application if it disables
the support for legacy IO drivers via:
#define CONFIGURE_IMFS_DISABLE_MKNOD
#define CONFIGURE_IMFS_DISABLE_MKNOD_DEVICE
Obsolete CONFIGURE_MAXIMUM_DEVICES. Remove BSP_MAXIMUM_DEVICES.
Update #3894.
Update #3898.
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updates #3849.
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These tests do not fit into the available memory.
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Use a specific test to enable the fast idle mode instead of using the
rtems_configuration_is_smp_enabled() workaround.
Update #3876.
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At least on GICv1 the interrupts 0 up to including 31 are so called
Peripheral Private Interrupts (PPIs). We have to initialize the
priority of the PPIs on secondary processors.
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drvmgr_get_dev_prefix returns 0 if a prefix was found.
Therefore the if condition needs to check for 0, i.e. DRVMGR_OK.
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This patch adds driver for Mini UART present in Raspberry Pi 3
and above, this UART is currently used as the primary UART in
these models.
The Mini UART is similar to ns16550, this driver is built
upon libchip/ns16550.
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This patch will allow the user to pass a function to calculate
the baud divisor.
This will allow for more flexibility, since for some BSPs
like raspberrypi, the calculation of baud divisor is different
from what is in the current driver.
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Place idle and MPCI stacks into extra linker sections. This can be
optionally used by applications to control the placement of the stacks.
Update #3835.
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This avoids to pull in via printk() the Termios support which pulls in
the file system support. This fixes a spconfig02 test failure.
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Update #3869.
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Update #3869.
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This uses the tx-threshold to reduce gaps in SPI transmissions.
Update #3869.
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