| Commit message (Collapse) | Author | Age | Files | Lines |
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Updates #4625.
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The memcpy() function may be not loaded at the time bsp_fdt_copy() is
called.
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A device tree blob must be aligned on an 8-byte boundary.
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The BSPs provide memory for the separate C Program Heap initialization
via _Memory_Get(). Most BSPs provide exactly one memory area. Only two
BSPs provide more than one memory area (arm/altera-cyclone-v and
bsps/powerpc/mpc55xxevb). Only if more than one memory area is
provided, there is a need to use _Heap_Extend(). Provide two
implementations to initialize the separate C Program Heap and let the
BSP select one of the implementations based on the number of provided
memory areas. This gets rid of a dependency on _Heap_Extend(). It
also avoids dead code sections for most BSPs.
Change licence to BSD-2-Clause according to file history.
Update #3053.
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The BSPs provide memory for the workspace initialization via
_Memory_Get(). Most BSPs provide exactly one memory area. Only two
BSPs provide more than one memory area (arm/altera-cyclone-v and
bsps/powerpc/mpc55xxevb). Only if more than one memory area is
provided, there is a need to use _Heap_Extend(). Provide two
implementations to initialize the workspace handler and let the BSP
select one of the implementations based on the number of provided memory
areas. This gets rid of a dependency on _Heap_Extend(). It also avoids
dead code sections for most BSPs.
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This adds the SMP function that supports spinup of additional CPU cores
using the ARM standard PSCI inteface. This interface is provided by QEMU
as well as ARM Trusted Firmware running in monitor mode (EL3) on ARMv7 and
AArch64 CPUs. This supports activation va SMC or HVC instructions
depending on BSP configuration.
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The heap protection is conditional.
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Update #4267.
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Change license to BSD-2-Clause according to file histories and
re-licensing agreement.
Update #3899.
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This adds a bsp_reset implementation based on the ARM PSCI
specification often present in ARMv8 systems.
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The cache of the fdt blob is flushed after copy. Therefore it should be
aligned.
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Replace the BSP_DIRTY_MEMORY BSP option with a CONFIGURE_DIRTY_MEMORY
configuration option.
Update #3843.
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The work area initialization was done by the BSP through
bsp_work_area_initialize(). This approach predated the system
initialization through the system initialization linker set. The
workspace and C program heap were unconditionally initialized. The aim
is to support RTEMS application configurations which do not need the
workspace and C program heap. In these configurations, the workspace
and C prgram heap should not get initialized.
Change all bsp_work_area_initialize() to implement _Memory_Get()
instead. Move the dirty memory, sbrk(), per-CPU data, workspace, and
malloc() heap initialization into separate system initialization steps.
This makes it also easier to test the individual initialization steps.
This change adds a dependency to _Heap_Extend() to all BSPs. This
dependency will be removed in a follow up change.
Update #3838.
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Directly use the CPU port API in boot_card() to allow tracing of the
higher level interrupt disable/enable routines, e.g.
_ISR_Local_disable() and _ISR_Local_enable(). Currently, there is no
configuration option to enable this. Below is a patch. It may be used
to investigate some nasty low level bugs in the system.
Update #3665.
diff --git a/cpukit/include/rtems/score/isrlevel.h b/cpukit/include/rtems/score/isrlevel.h
index c42451d010..46d361ddc2 100644
--- a/cpukit/include/rtems/score/isrlevel.h
+++ b/cpukit/include/rtems/score/isrlevel.h
@@ -40,6 +40,10 @@ extern "C" {
*/
typedef uint32_t ISR_Level;
+uint32_t rtems_record_interrupt_disable( void );
+
+void rtems_record_interrupt_enable( uint32_t level );
+
/**
* @brief Disables interrupts on this processor.
*
@@ -56,8 +60,7 @@ typedef uint32_t ISR_Level;
*/
#define _ISR_Local_disable( _level ) \
do { \
- _CPU_ISR_Disable( _level ); \
- RTEMS_COMPILER_MEMORY_BARRIER(); \
+ _level = rtems_record_interrupt_disable(); \
} while (0)
/**
@@ -72,10 +75,7 @@ typedef uint32_t ISR_Level;
* _ISR_Local_disable().
*/
#define _ISR_Local_enable( _level ) \
- do { \
- RTEMS_COMPILER_MEMORY_BARRIER(); \
- _CPU_ISR_Enable( _level ); \
- } while (0)
+ rtems_record_interrupt_enable( _level )
/**
* @brief Temporarily enables interrupts on this processor.
@@ -98,9 +98,8 @@ typedef uint32_t ISR_Level;
*/
#define _ISR_Local_flash( _level ) \
do { \
- RTEMS_COMPILER_MEMORY_BARRIER(); \
- _CPU_ISR_Flash( _level ); \
- RTEMS_COMPILER_MEMORY_BARRIER(); \
+ rtems_record_interrupt_enable( _level ); \
+ _level = rtems_record_interrupt_disable(); \
} while (0)
/
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- Use CamelCase as it is not used in our C code. Enables simple search and
replace.
- Prefix with "RTEMS" to aid deployment and integration. It aids
searching and sorting.
Update #3706.
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Remove the BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN hack. The interrupt
stacks are now allocated by the linker.
Update #3459.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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Use RTEMS_SYSINIT_ITEM() instead.
Update #2408.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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