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* bsp_specs: Delete last remnants of these.Joel Sherrill2021-11-291-0/+0
| | | | Updates #3937.
* build: Remove old build systemSebastian Huber2021-09-212-62/+0
| | | | | Close #3250. Close #4081.
* score: Canonicalize _CPU_Fatal_halt()Sebastian Huber2021-07-281-1/+2
| | | | | | | | Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it is a proper declaration of a function which does not return. Fix the type of the error code. If necessary, add the implementation to cpu.c. Implementing _CPU_Fatal_halt() as a function makes it possible to wrap this function for example to fully test _Terminate().
* bsps/irq: bsp_interrupt_facility_initialize()Sebastian Huber2021-07-271-3/+1
| | | | | | Do not return a status code in bsp_interrupt_facility_initialize() since this leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG assertions in bsp_interrupt_facility_initialize() if necessary.
* bsps/irq: bsp_interrupt_set_affinity()Sebastian Huber2021-07-262-4/+6
| | | | | | Return a status code for bsp_interrupt_set_affinity(). Update #3269.
* bsps/irq: bsp_interrupt_get_affinity()Sebastian Huber2021-07-262-2/+4
| | | | | | Return a status code for bsp_interrupt_get_affinity(). Update #3269.
* bsps/irq: bsp_interrupt_vector_disable()Sebastian Huber2021-07-261-1/+3
| | | | | | Return a status code for bsp_interrupt_vector_disable(). Update #3269.
* bsps/irq: bsp_interrupt_vector_enable()Sebastian Huber2021-07-261-1/+3
| | | | | | Return a status code for bsp_interrupt_vector_enable(). Update #3269.
* bsps/irq: Add rtems_interrupt_is_pending()Sebastian Huber2021-07-261-0/+11
| | | | | | Add a default implementation which just returns RTEMS_UNSATISFIED. Update #3269.
* bsps/irq: Add rtems_interrupt_get_attributes()Sebastian Huber2021-07-261-0/+8
| | | | | | | Add a default implementation which clears the attributes to zero and just returns RTEMS_SUCCESSFUL for valid parameters. Update #3269.
* bsps/irq: Add rtems_interrupt_raise()Sebastian Huber2021-07-261-0/+23
| | | | | | | | | Add rtems_interrupt_raise_on() and rtems_interrupt_clear(). Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
* bsps/irq: Add rtems_interrupt_vector_is_enabled()Sebastian Huber2021-07-261-0/+11
| | | | | | | Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
* bsps/irq: Remove BSP_INTERRUPT_VECTOR_MAXSebastian Huber2021-06-241-1/+0
| | | | | | This define is no longer used. Update #3269.
* bsps/irq: Add BSP_INTERRUPT_VECTOR_COUNTSebastian Huber2021-06-241-0/+1
| | | | | | | | | | | | | Assert BSP_INTERRUPT_VECTOR_MAX + 1 == BSP_INTERRUPT_VECTOR_COUNT. After building all BSPs with this patch, BSP_INTERRUPT_VECTOR_MAX can be removed and replaced by BSP_INTERRUPT_VECTOR_COUNT. The BSP_INTERRUPT_VECTOR_COUNT allows a default implementation which supports no interrupt vector at all. Using COUNT instead of MAX may avoid some interpretation issues, for example is the maximum value a valid vector number or not. Update #3269.
* bsps/irq: Remove BSP_INTERRUPT_VECTOR_MINSebastian Huber2021-06-241-2/+0
| | | | | | | | | | Remove BSP_INTERRUPT_VECTOR_MIN and unconditionally let interrupt vector numbers start with zero. The BSP_INTERRUPT_VECTOR_MIN == 0 invariant was tested by the previous commit and building all BSPs. Update #3269.
* bsps/riscv: Add per cpu clock interruptJan Sommer2021-03-231-10/+49
| | | | - Fixes failure of test smpclock01
* bsp/riscv: Re-license to BSD-2-ClauseSebastian Huber2021-02-091-10/+37
| | | | | | Change license to BSD-2-Clause according to file history. Update #3053.
* bsps: Replace bsp_specs with an empty fileSebastian Huber2021-01-281-9/+0
| | | | | | | This fixes an issue with the latest tool chain which adds the default linker script in the endfile specification. Update #3250.
* bsps/riscv: Add bsp_fdt_map_intr()Sebastian Huber2020-09-231-0/+6
| | | | This function is required by libbsd.
* riscv: Make sifive_test finisher 4 bytesHesham Almatary2020-09-171-1/+1
| | | | | | QEMU is now stricter with MMIO sizes and accesses. uintptr_t on RV64 is 8 bytes and generates an sd instruction that Store/AMO faults because sifive_test MMIO expects 4 bytes accesses.
* htif_console_handler is defined in htif.cHesham Almatary2020-09-061-1/+1
| | | | closes #4069.
* Use RTEMS_SYSINIT_ORDER_LAST_BUT_5Sebastian Huber2020-02-041-1/+1
| | | | | | | | Use RTEMS_SYSINIT_ORDER_LAST_BUT_5 instead of RTEMS_SYSINIT_ORDER_LAST to allow applications and support functions to place system initialization handlers behind the standard handlers. Update #3838.
* Regenerate headers.amSebastian Huber2019-11-291-0/+1
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* bsp/riscv: Fix format and warningsSebastian Huber2019-11-142-45/+27
| | | | Update #3785.
* bsp/riscv: Fix use of uninitialized integerSebastian Huber2019-11-141-6/+1
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* bsp/riscv: riscv_get_core_frequency()Sebastian Huber2019-11-142-43/+23
| | | | | | | Always provide this function. Return 0 by default. Fix formatting. Simplify function. Update #3785.
* bsps/riscv: UART - Read reg-shift from DTB to properly set/get registersHesham Almatary2019-10-301-2/+13
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* riscv: Add new BSP cfg variants to be built with llvm/clangHesham Almatary2019-10-278-0/+112
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* riscv: add freedom E310 Arty A7 bspPragnesh Patel2019-10-237-5/+312
| | | | | | | Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board. Update #3785. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* score: Rename _SMP_Get_processor_count()Sebastian Huber2019-04-111-9/+9
| | | | | | | Rename _SMP_Get_processor_count() in _SMP_Get_processor_maximum() to be in line with the API level rtems_scheduler_get_processor_maximum(). Update #3732.
* bsps: Adjust bsp.h Doxygen groupsSebastian Huber2019-03-081-0/+20
| | | | Update #3706.
* riscv: add griscv bspJiri Gaisler2019-01-223-532/+5
| | | | Update #3678.
* bsp/riscv: Clear boot command lineSebastian Huber2019-01-081-0/+1
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* score: Rename interrupt stack symbolsSebastian Huber2018-11-081-3/+3
| | | | | | | | | | | | | Rename * _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin, * _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and * _Configuration_Interrupt_stack_size in _ISR_Stack_size. Move definitions to <rtems/score/isr.h>. The new names are considerable shorter and in the right namespace. Update #3459.
* riscv: Allow platforms with no PLIC to proceedHesham Almatary2018-09-171-0/+5
| | | | Spike simulator and QEMU's spike_v1.10 don't have a PLIC
* bsp/riscv: Add missing BSP variantSebastian Huber2018-08-021-0/+9
| | | | Update #3433.
* bsp/riscv: Fix build with RTEMS_SMP undefinedSebastian Huber2018-08-023-12/+10
| | | | Update #3433.
* bsp/riscv: Fix a synchronization issue for PLICSebastian Huber2018-08-021-0/+8
| | | | Update #3433.
* bsp/riscv: Remove unused variableSebastian Huber2018-08-011-4/+0
| | | | Update #3433.
* bsp/riscv: Add NS16750 support to console driverSebastian Huber2018-08-011-36/+74
| | | | Update #3433.
* bsp/riscv: Initialize FPU depending on ISASebastian Huber2018-08-011-1/+4
| | | | | | Initialize fcsr to zero for a defined rounding mode. Update #3433.
* bsp/riscv: Fix clock driverSebastian Huber2018-08-011-17/+49
| | | | | | Do not assume that mtime is zero at boot time. Update #3433.
* bsp/riscv: Fix inter-processor interruptsSebastian Huber2018-07-271-1/+7
| | | | | | | | The previous version worked only on a patched Qemu. Writes to mip are illegal according to the The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Privileged Architecture Version 1.10. Update #3433.
* riscv: Rework CPU counter supportSebastian Huber2018-07-271-4/+18
| | | | Update #3433.
* bsp/riscv: Use interrupt driven NS16550 driverSebastian Huber2018-07-251-1/+9
| | | | Update #3433.
* bsp/riscv: Add PLIC supportSebastian Huber2018-07-254-2/+258
| | | | Update #3433.
* bsp/riscv: Add simple SMP support to clock driverSebastian Huber2018-07-251-0/+2
| | | | | | This is a hack. The clock interrupt should be handled by each hart. Update #3433.
* bsp/riscv: Use CPU counter btimerSebastian Huber2018-07-251-68/+0
| | | | Update #3433.
* bsp/riscv: Add basic SMP startupSebastian Huber2018-07-256-26/+295
| | | | Update #3433.
* riscv: Add CLINT and PLIC supportSebastian Huber2018-07-253-62/+4
| | | | | | The CLINT and PLIC need some per-processor state. Update #3433.
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