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2024-03-27bsps: Move declarations to <bsp/irq-generic.h>Sebastian Huber1-1/+0
Move declarations of bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() to <bsp/irq-generic.h>. Canonicalize the <bsp/irq.h> includes. Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if needed (usually RTEMS_SMP). Provide stub implementations for i386 to fix build errors.
2023-05-20Update company nameSebastian Huber1-1/+1
The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
2023-01-12riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORTSebastian Huber1-7/+11
Low-end configurations may want to have the HTIF support removed. Enable the option by default. Fix formatting. Fix node validity checks. Updates #4779.
2022-12-23RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORTHesham Almatary1-6/+9
Updates #4779
2022-11-23bsps/riscv: Simplify PLIC supportSebastian Huber1-28/+30
In uniprocessor configurations there is no need to take interrupt affinities into account for the interrupt vector enable/disable.
2022-11-23bsps/riscv: Fix PLIC enable register countSebastian Huber1-3/+5
2022-11-23bsps/riscv: Add riscv_plic_cpu_0_init()Sebastian Huber1-13/+23
Move boot processor initialization of PLIC to separate function.
2022-11-11bsps/riscv: Fix software interrupt dispatchingSebastian Huber1-2/+4
In SMP configurations, there may be no software interrupt handler installed when the software interrupt is processed. Add the new interrupt handler dispatch variant bsp_interrupt_handler_dispatch_unlikely() for this special case.
2022-11-10bsps/riscv: Fix PLIC enable register countSebastian Huber1-2/+2
Each PLIC enable register has 32 bits, so we have to divide by 32.
2022-11-10bsps/riscv: Skip init on not configured processorsSebastian Huber1-0/+11
2022-11-10bsps/riscv: Simplify riscv_plic_init()Sebastian Huber1-30/+39
2022-11-10bsps/riscv: Simplify riscv_clint_init()Sebastian Huber1-14/+25
2022-11-10bsps/riscv: Always dispatch software interruptsSebastian Huber1-3/+2
This helps to run the interrupt API validation tests.
2022-11-10bsps/riscv: bsp_interrupt_get/set_affinity()Sebastian Huber1-13/+6
Provide bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if RTEMS_SMP is enabled. Replace fatal error with a status code.
2022-11-10bsps/riscv: bsp_interrupt_raise_on()Sebastian Huber1-4/+20
Implement bsp_interrupt_raise_on() and bsp_interrupt_raise().
2022-11-10bsps/riscv: bsp_interrupt_is_pending()Sebastian Huber1-2/+25
Implement this function.
2022-11-10bsps/riscv: bsp_interrupt_get_attributes()Sebastian Huber1-0/+15
Implement this function.
2022-11-10bsps/riscv: Improve bsp_interrupt_vector_disable()Sebastian Huber1-0/+8
Add support for hart-specific software and timer interrupts.
2022-11-10bsps/riscv: Improve bsp_interrupt_vector_enable()Sebastian Huber1-0/+8
Add support for hart-specific software and timer interrupts.
2022-11-10bsps/riscv: bsp_interrupt_vector_is_enabled()Sebastian Huber1-2/+47
Implement this function.
2022-11-10bsps/riscv: bsp_interrupt_is_valid_vector()Sebastian Huber1-1/+16
Implement this function.
2022-09-20bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari1-0/+81
The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
2021-07-27bsps/irq: bsp_interrupt_facility_initialize()Sebastian Huber1-3/+1
Do not return a status code in bsp_interrupt_facility_initialize() since this leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG assertions in bsp_interrupt_facility_initialize() if necessary.
2021-07-26bsps/irq: bsp_interrupt_set_affinity()Sebastian Huber1-3/+5
Return a status code for bsp_interrupt_set_affinity(). Update #3269.
2021-07-26bsps/irq: bsp_interrupt_get_affinity()Sebastian Huber1-1/+3
Return a status code for bsp_interrupt_get_affinity(). Update #3269.
2021-07-26bsps/irq: bsp_interrupt_vector_disable()Sebastian Huber1-1/+3
Return a status code for bsp_interrupt_vector_disable(). Update #3269.
2021-07-26bsps/irq: bsp_interrupt_vector_enable()Sebastian Huber1-1/+3
Return a status code for bsp_interrupt_vector_enable(). Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_is_pending()Sebastian Huber1-0/+11
Add a default implementation which just returns RTEMS_UNSATISFIED. Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_get_attributes()Sebastian Huber1-0/+8
Add a default implementation which clears the attributes to zero and just returns RTEMS_SUCCESSFUL for valid parameters. Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_raise()Sebastian Huber1-0/+23
Add rtems_interrupt_raise_on() and rtems_interrupt_clear(). Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_vector_is_enabled()Sebastian Huber1-0/+11
Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
2019-04-11score: Rename _SMP_Get_processor_count()Sebastian Huber1-9/+9
Rename _SMP_Get_processor_count() in _SMP_Get_processor_maximum() to be in line with the API level rtems_scheduler_get_processor_maximum(). Update #3732.
2018-09-17riscv: Allow platforms with no PLIC to proceedHesham Almatary1-0/+5
Spike simulator and QEMU's spike_v1.10 don't have a PLIC
2018-08-02bsp/riscv: Fix build with RTEMS_SMP undefinedSebastian Huber1-4/+0
Update #3433.
2018-08-02bsp/riscv: Fix a synchronization issue for PLICSebastian Huber1-0/+8
Update #3433.
2018-08-01bsp/riscv: Remove unused variableSebastian Huber1-4/+0
Update #3433.
2018-07-27bsp/riscv: Fix inter-processor interruptsSebastian Huber1-1/+7
The previous version worked only on a patched Qemu. Writes to mip are illegal according to the The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Privileged Architecture Version 1.10. Update #3433.
2018-07-25bsp/riscv: Add PLIC supportSebastian Huber1-1/+240
Update #3433.
2018-07-25bsp/riscv: Add basic SMP startupSebastian Huber1-0/+56
Update #3433.
2018-07-25riscv: Rework exception handlingSebastian Huber1-3/+25
Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() functions. Applications can install an exception handler via the fatal error handler to handle synchronous exceptions. Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must be provided by the BSP. Update #3433.
2018-06-28bsp/riscv: Remove bsp_interrupt_handler_default()Sebastian Huber1-9/+0
It duplicated the default implementation. Update #3433.
2018-06-27bsp/riscv_generic: Rename to "riscv"Sebastian Huber1-0/+0
Update #3433.
2018-04-23bsps: Move interrupt controller support to bspsSebastian Huber1-0/+0
This patch is a part of the BSP source reorganization. Update #3285.
2018-03-27bsps/riscv: Fix warningsSebastian Huber1-6/+1
2017-11-01bsp: Make riscv_generic work for both riscv32 and riscv64 - v2Hesham Almatary1-0/+0
Update #3109
2017-10-28bsp: Add new riscv_generic bsp v3Hesham Almatary1-8/+9
* Only runs/tested on simulator/spike. * Ticker, hello, capture work proprely * Tested via RTEMS Tester, Passed: 525/565 (92%) Update #3109
2017-06-20bsps: Improve interrupt vector enable/disable APISebastian Huber1-4/+4
Change bsp_interrupt_vector_enable() and bsp_interrupt_vector_disable() to not return a status code. Add bsp_interrupt_assert() and use it to validate the vector number in the vector enable/disable implementations.
2017-04-25rtems/inttypes.h epiphany_sim/irq/irq.c: Add PRIdrtems_vector_number and use itJoel Sherrill1-1/+3
2015-05-21Epiphany: Add the first epiphany_sim BSP v4Hesham ALMatary1-30/+24
This BSP in intended to run on the simulator that should be built from RSB. When building RTEMS for Epiphany --disable-networking must be provided part of the configure command.
2015-05-21cpukit: Add Epiphany architecture port v4Hesham ALMatary1-12/+39
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