Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | riscv: add griscv bsp | Jiri Gaisler | 2019-01-22 | 1 | -0/+5 |
* | bsp/riscv: Fix clock driver | Sebastian Huber | 2018-08-01 | 1 | -17/+49 |
* | riscv: Rework CPU counter support | Sebastian Huber | 2018-07-27 | 1 | -4/+18 |
* | bsp/riscv: Add simple SMP support to clock driver | Sebastian Huber | 2018-07-25 | 1 | -0/+2 |
* | bsp/riscv: Add basic SMP startup | Sebastian Huber | 2018-07-25 | 1 | -8/+2 |
* | riscv: Add CLINT and PLIC support | Sebastian Huber | 2018-07-25 | 1 | -5/+4 |
* | bsp/riscv: Add and use riscv_fdt_get_address() | Sebastian Huber | 2018-07-25 | 1 | -15/+31 |
* | riscv: Rework exception handling | Sebastian Huber | 2018-07-25 | 1 | -5/+14 |
* | riscv: Implement CPU counter | Sebastian Huber | 2018-07-06 | 1 | -10/+2 |
* | riscv: Avoid namespace pollution | Sebastian Huber | 2018-06-28 | 1 | -0/+1 |
* | bsp/riscv: Rework clock driver | Sebastian Huber | 2018-06-28 | 1 | -41/+67 |
* | bsp/riscv_generic: Rename to "riscv" | Sebastian Huber | 2018-06-27 | 1 | -0/+122 |