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* bsps/irq: Use BSP_INTERRUPT_VECTOR_COUNTSebastian Huber2021-06-241-1/+1
| | | | | | Use BSP_INTERRUPT_VECTOR_COUNT instead of BSP_INTERRUPT_VECTOR_MAX. Update #3269.
* bsps/irq: Remove BSP_INTERRUPT_VECTOR_MINSebastian Huber2021-06-241-1/+1
| | | | | | | | | | Remove BSP_INTERRUPT_VECTOR_MIN and unconditionally let interrupt vector numbers start with zero. The BSP_INTERRUPT_VECTOR_MIN == 0 invariant was tested by the previous commit and building all BSPs. Update #3269.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-231-56/+0
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* bsps: Remove gicvx_interrupt_dispatch()Sebastian Huber2020-12-161-5/+0
| | | | | | Avoid one level of indirection. Update #4202.
* bsps: Move ARM GICv2 driver to bsps/sharedKinsey Moore2020-12-022-287/+1
| | | | | This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code.
* bsps: Break out AArch32 GICv3 supportKinsey Moore2020-10-053-330/+62
| | | | | This breaks out AArch32-specific code so that the shared GICv3 code can be reused by other architectures.
* arm: ARMv7-M statically initialized vector tableSebastian Huber2020-04-031-18/+32
| | | | | | | Statically initialize the ARMv7-M vector table to allow a placement in ROM with read-only MPU settings. Change licence to BSD-2-Clause in some files.
* bsps/arm: Initialize priorities of PPIsSebastian Huber2020-02-241-0/+6
| | | | | | At least on GICv1 the interrupts 0 up to including 31 are so called Peripheral Private Interrupts (PPIs). We have to initialize the priority of the PPIs on secondary processors.
* bsps/arm/shared: Add GICv3 implementationKinsey Moore2020-01-172-0/+345
| | | | | | | | | This adds support for the GICv3 interrupt controller along with the redistributor to control SGIs and PPIs which wasn't present in GICv2 implementations. GICv3 implementations only optionally support memory-mapped GICC interface interaction and require system register access be implemented, so the GICC interface is accessed only through system registers.
* bsps/arm: Add BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0Sebastian Huber2019-02-281-3/+51
| | | | | | | | | | | | | | | | | The following variants * GICv1 with Security Extensions, * GICv2 without Security Extensions, or * within Secure processor mode have the ability to assign group 0 or 1 to individual interrupts. Group 0 interrupts can be configured to raise an FIQ exception. This enables the use of NMIs with respect to RTEMS. BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 define. Use arm_gic_irq_set_group() to change the group of an interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is defined).
* bsps/arm: Support GIC group 0/1Sebastian Huber2019-02-281-1/+37
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* bsps: Move interrupt controller support to bspsSebastian Huber2018-04-233-0/+279
This patch is a part of the BSP source reorganization. Update #3285.
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