rtems - RTEMS Kernel, file-systems, drivers, BSPs, samples, and testsuite.

	Commit message (Collapse)	Author	Files	Lines
2023-05-26	bsps: Improve Doxygen file comments	Sebastian Huber	1	-3/+4

2023-05-20	Update company name	Sebastian Huber	1	-1/+1
	The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
2022-07-08	bsps/arm/shared: Change license to BSD-2	Joel Sherrill	1	-3/+22
	Updates #3053.
2022-03-10	bsps/arm/: Scripted embedded brains header file clean up	Joel Sherrill	1	-6/+0
	Updates #4625.
2019-03-08	bsps: Adjust shared Doxygen groups	Sebastian Huber	1	-1/+1
	Update #3706.
2018-12-21	ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS	Sebastian Huber	1	-1/+0
	Remove this superfluous define. Update #3667.
2018-01-31	bsps: Rework cache manager implementation	Sebastian Huber	1	-2/+0
	The previous cache manager support used a single souce file (cache_manager.c) which included an implementation header (cache_.h). This required the use of specialized include paths to find the right header file. Change this to include a generic implementation header (cacheimpl.h) in specialized source files. Use the following directories and files: * bsps/shared/cache * bsps/@RTEMS_CPU@/shared/cache * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c Update #3285.
2016-07-20	arm/bsps: CP15 and basic cache support entire cache clean for more ↵	Pavel Pisa	1	-1/+5
	architecture variants now. Next cache operations should work on most of cores now rtems_cache_flush_entire_data() rtems_cache_invalidate_entire_data() rtems_cache_invalidate_entire_instruction() Instruction cache invalidate works on the first level for now only. Data cacache operations are extended to ensure flush/invalidate on all cache levels. The CP15 arm_cp15_data_cache_clean_all_levels() function extended to continue through unified levels too (ctype = 4).
2016-07-04	bsps/arm: basic on core cache support changed to use l1 functions.	Pavel Pisa	1	-42/+29
	The basic data and instruction rage functions should be compatible for all ARMv4,5,6,7 functions. On the other hand, some functions are not portable, for example arm_cp15_data_cache_test_and_clean() and arm_cp15_data_cache_invalidate() for all versions and there has to be specialized version for newer cores. arm_cache_l1_properties_for_level uses CCSIDR which is not present on older chips. Actual version is only experimental, needs more changes and problem has been found on RPi1 with dlopen so there seems to be real problem.
2015-07-21	bsps/arm: Update due to API changes	Sebastian Huber	1	-4/+4

2014-11-20	bsps/arm: L1 cache support changes	Sebastian Huber	1	-16/+21

2014-06-06	bsps/arm: Change L2 cache initialization	Sebastian Huber	1	-47/+0
	Do not touch the L1 caches since they have been initialized by the start hooks.
2014-06-05	bsps/arm: Simplify L1 caches support	Sebastian Huber	1	-55/+12
	Delete superfluous/incorrect interrupt disable/enable.
2014-04-17	bsp/arm: Add cache size methods	Ralf Kirchner	1	-0/+33
	Add new methods which deliver the cache sizes of for supported cache levels.
2014-04-17	bsp/arm: Remove unused cache store methods	Ralf Kirchner	1	-9/+0

2014-04-17	bsp/arm: Correct cache misalignment handling	Ralf Kirchner	1	-6/+6
	Correct misalignment handling and prepare for locking.
2014-04-17	bsp/arm: Consistenly same handling for flushing	Ralf Kirchner	1	-2/+2
	It is importeant to consistently apply the same handling for flushing within level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
2014-04-17	bsp/arm: RTEMS_SMP to arm erratum 764369 detection	Ralf Kirchner	1	-8/+4
	Move the RTEMS_SMP conditional compilation to the detection method of arm erratum 764369
2014-04-17	bsp/arm: Cleanup L1 cache	Ralf Kirchner	1	-2/+2

2014-03-13	bsp/arm: Add handling for level 2 L2C-310 cache controller	Ralf Kirchner	1	-0/+483
	arm-l2c-310/cache_.h contains the handling for the L2C-310 level 2 cache controller from arm. It references the arm level 1 cache handling in the new file arm-cache-l1.h.