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* bsps: Support RTEMS_NOINIT in linkcmdsSebastian Huber2021-05-022-1/+9
| | | | Update #3866.
* bsps/arm: ARMV7_CP15_START_WORKSPACE_ENTRY_INDEXSebastian Huber2021-04-291-1/+1
| | | | | | | Change the ARMV7_CP15_START_WORKSPACE_ENTRY_INDEX value to be in line with the workspace entry in ARMV7_CP15_START_DEFAULT_SECTIONS. Close #4395.
* bsps/arm: Rely on initialized vector tableSebastian Huber2020-12-231-5/+4
| | | | | | | The arm_cp15_set_exception_handler() is a complicated function which should be avoided if possible. Update #4202.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-231-0/+68
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* bsps/arm: Add arm-data-cache-loop-set-way.hSebastian Huber2020-12-231-0/+96
| | | | | | This makes it possible to reuse this loop. Update #4202.
* bsps/arm: Remove optional start hook argumentsSebastian Huber2020-12-231-11/+2
| | | | | | | The start hook arguments are not used by a BSP. Removing them avoids the need for a stack during the very early system initialization. Update #4202.
* bsps/arm: Invalidate branch predictors earlierSebastian Huber2020-12-231-2/+0
| | | | | | | Make sure the branch predictors are invalidated before the first branch is executed. Update #4202.
* bsps/arm: Set VBAR in start.SSebastian Huber2020-12-232-79/+4
| | | | | | | | | | Set the VBAR to the vector table in the start section before bsp_start_hook_0() is called to earlier handle exceptions in RTEMS. Set the VBAR to the normal vector table in start.S for the main processor. Secondary processors set it in bsp_start_hook_0(). Update #4202.
* bsps/arm: Fix MMU configurationSebastian Huber2020-12-152-0/+8
| | | | Update #4184.
* bsps/arm/imx*: Fix location of shared headersChristian Mauderer2020-12-144-0/+355
| | | | | | | When moving the headers from the imx BSP to the shared area, the wrong directory has been selected. This patch fixes that problem. Update #4180
* bsps/arm: Fix MMU small pages supportJan Sommer2020-12-111-1/+1
| | | | | | - For small tables only round to the next 4kiB instead of 1MiB Close #4184.
* bsps: Move zynq-uart to bsps/sharedKinsey Moore2020-12-022-241/+0
| | | | | This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to accomodate use by AArch64 BSPs.
* bsps/arm: Add workaround for Errata 794072Sebastian Huber2020-10-161-0/+16
| | | | | | | | Add a workaround for Cortex-A9 Errata 845369: A short loop including a DMB instruction might cause a denial of service on another which executes a CP15 broadcast operation. Close #4115.
* bsps/arm: Workaround for Errata 845369Sebastian Huber2020-10-161-0/+15
| | | | | | | Add a workaround for Cortex-A9 Errata 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption. Update #4115.
* bsps: Break out AArch32 GICv3 supportKinsey Moore2020-10-055-687/+1
| | | | | This breaks out AArch32-specific code so that the shared GICv3 code can be reused by other architectures.
* Move ARM PL011 UART driverKinsey Moore2020-10-052-181/+0
| | | | This UART driver is now needed for BSPs other than ARM.
* bsps/arm: Use RTEMS_SECTION()Sebastian Huber2020-09-171-6/+12
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* bsps/arm/shared: Add GICv3 implementationKinsey Moore2020-01-172-9/+82
| | | | | | | | | This adds support for the GICv3 interrupt controller along with the redistributor to control SGIs and PPIs which wasn't present in GICv2 implementations. GICv3 implementations only optionally support memory-mapped GICC interface interaction and require system register access be implemented, so the GICC interface is accessed only through system registers.
* bsps/arm: Define index of the workspace entry.Christian Mauderer2020-01-071-0/+2
| | | | | | The imx BSP contained a hack to change the workspace entry of the MMU table. This makes the used define visible for other BSPs too so that the same hack can be used for example in raspberry pi too.
* bsps/arm: Add support for small pages MMUSebastian Huber2019-10-311-9/+48
| | | | | | | The small page MMU support reduces the granularity for memory settings through the MMU from 1MiB sections to 4KiB small pages. Enable it by default on the realview_pbx_a9_qemu BSP.
* bsp/beagle: Partial re-write of I2C driver.Christian Mauderer2019-06-291-11/+24
| | | | | | | | | The old driver worked well for EEPROMS with the RTEMS EEPROM driver. But it had problems with a lot of other situations. Although it's not a direct port, the new driver is heavily modeled after the FreeBSD ti_i2c driver. Closes #3764.
* bsp/zynq-uart: Move Zynq UART driver to shared directoryJeff Kubascik2019-04-112-0/+241
| | | | | | This driver will be shared with the xilinx-zynqmp BSP. Update #3682.
* bsps/arm: Optimize ARMv7-M CPU counterSebastian Huber2019-04-091-4/+5
| | | | Update #3456.
* bsps/arm: Fix ARMv7-M CPU counterSebastian Huber2019-04-091-0/+1
| | | | | | | Read the current counter value again after we know that we had an underflow. Update #3456.
* bsps/arm: Adjust CMSIS Doxygen groupsSebastian Huber2019-03-084-0/+7
| | | | Update #3706.
* bsps: Adjust shared Doxygen groupsSebastian Huber2019-03-0816-16/+16
| | | | Update #3706.
* bsps: Adjust bsp.h Doxygen groupsSebastian Huber2019-03-085-10/+10
| | | | Update #3706.
* bsps/arm: Add BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0Sebastian Huber2019-02-281-0/+3
| | | | | | | | | | | | | | | | | The following variants * GICv1 with Security Extensions, * GICv2 without Security Extensions, or * within Secure processor mode have the ability to assign group 0 or 1 to individual interrupts. Group 0 interrupts can be configured to raise an FIQ exception. This enables the use of NMIs with respect to RTEMS. BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 define. Use arm_gic_irq_set_group() to change the group of an interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is defined).
* bsps/arm: Fix typoSebastian Huber2019-02-281-1/+1
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* bsps/arm: Support GIC group 0/1Sebastian Huber2019-02-283-4/+54
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* Remove explicit file names from @fileSebastian Huber2019-02-287-7/+7
| | | | | | This makes the @file documentation independent of the actual file name. Update #3707.
* arm/beagle: SPI driverPierre-Louis Garnier2019-02-271-1/+92
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* bsps/arm: Fix PL111 register define re-definitionSebastian Huber2018-08-201-1/+1
| | | | Close #3502.
* _SMP_Start_multitasking_on_secondary_processor()Sebastian Huber2018-07-251-1/+1
| | | | | Pass current processor control as first parameter to make dependency more explicit.
* bsps: Fix function declaration warningsSebastian Huber2018-07-241-2/+2
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* bsps/arm: Include missing header fileSebastian Huber2018-07-051-0/+1
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* Rework initialization and interrupt stack supportSebastian Huber2018-06-271-22/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Statically initialize the interrupt stack area (_Configuration_Interrupt_stack_area_begin, _Configuration_Interrupt_stack_area_end, and _Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the interrupt stack area in a special section ".rtemsstack.interrupt". Let BSPs define the optimal placement of this section in their linker command files (e.g. in a fast on-chip memory). This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the low level initialization code has all information available via global symbols. This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define superfluous, since the interrupt stacks are allocated by confdefs.h for all architectures. There is no need for BSP-specific linker command file magic (except the section placement), see previous ARM linker command file as a bad example. Remove _CPU_Install_interrupt_stack(). Initialize the hardware interrupt stack in _CPU_Initialize() if necessary (e.g. m68k_install_interrupt_stack()). The optional _CPU_Interrupt_stack_setup() is still useful to customize the registration of the interrupt stack area in the per-CPU information. The initialization stack can reuse the interrupt stack, since * interrupts are disabled during the sequential system initialization, and * the boot_card() function does not return. This stack resuse saves memory. Changes per architecture: arm: * Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases. * Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp. bfin: * Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value. lm32, m32c, mips, nios2, riscv, sh, v850: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. m68k: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. powerpc: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. * Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA). sparc: * Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM. Update #3459.
* arm: Simplify CPU counter supportSebastian Huber2018-06-151-0/+78
| | | | | | | | | | Use the standard ARMv7-M systick module for the ARMv7-M CPU counter instead of DWT counter since the DWT counter is affected by power saving states. Use an inline function for _CPU_Counter_difference() for all ARM BSPs. Update #3456.
* Add _CPU_Counter_frequency()Sebastian Huber2018-06-151-9/+0
| | | | | | | | | | Add rtems_counter_frequency() API function. Use it to initialize the counter value converter via the new system initialization step (RTEMS_SYSINIT_CPU_COUNTER). This decouples the counter implementation and the counter converter. It avoids an unnecessary pull in of the 64-bit integer division from libgcc. Update #3456.
* bsp/arm-a8core-start.h: Add void return type to fix warningJoel Sherrill2018-03-161-2/+2
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* Remove make preinstallChris Johns2018-01-2536-0/+8729
A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254.
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