diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-02-28 10:40:10 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-02-28 11:52:30 +0100 |
| commit | 76918e180a540c3705ab50300117345b024fdc0f (patch) | |
| tree | 6b5fe30e2dd214aa05fda9d141107f39ecb9cdf4 /bsps/arm/include | |
| parent | bsps/arm: Fix typo (diff) | |
| download | rtems-76918e180a540c3705ab50300117345b024fdc0f.tar.bz2 | |
bsps/arm: Add BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
The following variants
* GICv1 with Security Extensions,
* GICv2 without Security Extensions, or
* within Secure processor mode
have the ability to assign group 0 or 1 to individual interrupts. Group
0 interrupts can be configured to raise an FIQ exception. This enables
the use of NMIs with respect to RTEMS.
BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
define. Use arm_gic_irq_set_group() to change the group of an
interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is
defined).
Diffstat (limited to 'bsps/arm/include')
| -rw-r--r-- | bsps/arm/include/bsp/arm-gic-irq.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/bsps/arm/include/bsp/arm-gic-irq.h b/bsps/arm/include/bsp/arm-gic-irq.h index fa0d63d063..b3e893de72 100644 --- a/bsps/arm/include/bsp/arm-gic-irq.h +++ b/bsps/arm/include/bsp/arm-gic-irq.h @@ -98,6 +98,9 @@ static inline rtems_status_code arm_gic_irq_generate_software_irq( dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter) | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets) +#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 + | GIC_DIST_ICDSGIR_NSATT +#endif | GIC_DIST_ICDSGIR_SGIINTID(vector); } else { sc = RTEMS_INVALID_ID; |