| Commit message (Collapse) | Author | Age | Files | Lines |
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The address of the nandpsu peripheral is specific to the ZynqMP SoC and
not relevant to other devices that might have one or more instances of
this peripheral.
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Add ref-clock-num identifiers to the device tree to ensure that
interfaces use the correct clocks even when some are not used due to
unconnected MII busses. This also adjusts the default ZynqMP PHY
attachment to RGMII-ID which was the default before device trees were
introduced.
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Tested on VCK190
Updates #4762
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This changes the ZynqMP device tree parsing over to direct libfdt calls
to avoid inclusion of malloc() in the base BSP which currently causes
sp01 to fail due to unexpected use of TLS space.
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In the original implementation, level -1 was unused and all levels could
have block-like descriptors (level 2 block descriptors are called page
descriptors). When support for level -1 page tables was added the
constraint on level -1 block descriptors was not honored. This prevents
block descriptors from being mapped at level -1 since the hardware will
not map them properly.
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RTEMS may be booted from a dirty environment. Ensure that FPU trap
settings are consistent.
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This adds a BSP variant for the ZynqMP BSP family to support the
Innoflight CFC-400X platform. To properly support the CFC-400X, device
trees were added to the ZynqMP platform due to both the optional
management interface as well as alternate physical configuration of the
ethernet interfaces.
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This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently
only LP64 ABI is supported. ILP32 is not supported. RAM starts from 0x80000 in
64Bit kernel mode and MMU from 0x0. All Raspberrypi Pi 4B models and Raspberry
Pi 400 are supported. All the IRQs are similiar to the older Raspberry pi 2 ARM
BSP.
Raspberry Pi 4B has 2 types of UARTs. Only PL011 serial is supported currently.
Mini-UART is not supported. Mini-UART is default UART on the board so it needs
to be disabled by adding "dtoverlay=disable-bt" to the config.txt. No support
for additional 4 PL011-UARTs on the board.
The raspberrypi.h includes many of the address required for the future
development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore
Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.
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The .data.rel.ro* linker input section pattern accidentally matches with
writeable data those symbol name starts with "ro".
Close #4701.
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- Support DDRMC0 region 0 up to 2G in size
- Support DDRMC0 region 1 with DDR memory greater than 2G
up to the DDRMC0 max amount
- Extend the heap with region 1's memory
Closes #4684
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Update #4684
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This alters the AArch64 page table generation and mapping code and MMU
configuration to use page table level 0 in addition to levels 1, 2, and
3. This allows the mapping of up to 48 bits of memory space and is the
maximum that can be mapped without relying on additional processor
extensions. Mappings are restricted based on the number of physical
address bits that the CPU supports.
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This section was added recently and must be mapped to be accessed
without generating an exception.
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Sort the .noinit* input sections by name first, then by alignment if two
sections have the same name. This allows the placement of begin/end symbols to
initialize some areas with a special value.
Update #4678.
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There were two bugs with MMU page use that were partially hiding each
other. The linker script page table section was 4x the size it needed to
be and the page table allocation routine was allocating pages PTRSIZE
times larger than it needed to. On ILP32, this resulted in incorrect but
functional allocation. On LP64, this resulted in allocation failures
earlier than expected.
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- Any page tables need to be flushed if the cache is enabled.
Disabling the cache may only be available in secure mode.
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Updates #4664
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Always start the executive in Exception Level 1, Non-Secure mode.
If we boot in EL3 Secure with GICv3 then we have to initialize
the distributor and redistributor to set up G1NS interrupts
early in the boot sequence before stepping down from EL3S to EL1NS.
Now there is no need to distinguish between secure and non-secure
world execution after the primary core boots, so get rid of the
AARCH64_IS_NONSECURE configuration option.
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The AArch64 cache implementation does not define
rtems_cache_disable_data(), but declares that it does via
CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of
_CPU_cache_disable_data() is sufficient to enable this functionality
without the erroneous cache feature flag.
Closes #4569
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Fixing the debug mask flag broke nested interrupts. This restores that
functionality.
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This adds support for libdebugger under AArch64 using software
breakpoints and the single-step execution mode present in all AArch64
CPUs.
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Debug events should be masked at least until after the first context
switch and should usually be masked until a debugger is attached for
application debugging.
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The existing code is functional but inccorrect and blindly modifies the
other masking bits. It is important to preserve those other bits since
they control masking of important system events.
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Certain input parameters for MMU mapping operations could cause an
infinite recursion if block end boundaries didn't align to 4k. This
ensures that recursion descent does not exceed 2 levels and instead
rounds up to the nearest 4k block if necessary.
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This moves the AArch64 MMU memory type definitions into cpukit for use
by libdebugger since remapping of memory is required to insert software
breakpoints.
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This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
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GICv2 can support up to 1024 interrupts, but ZynqMP hardware is only
configured for 192 interrupts.
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Added I2C drivers for ZynqMP and updated build system accordingly.
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- Wait for the tx holding register to empty in a tx flush
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Update #3269.
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The existing fix for the ZynqMP UART hardware bug only caught the vast
majority of instances where it could occur. To fully fix the data
corruption, this fix must be applied after every baud rate change. This
makes the logic reset and kick apply in any locations where the baud
rate could be changed.
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This define is no longer used.
Update #3269.
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Assert BSP_INTERRUPT_VECTOR_MAX + 1 == BSP_INTERRUPT_VECTOR_COUNT.
After building all BSPs with this patch, BSP_INTERRUPT_VECTOR_MAX can be
removed and replaced by BSP_INTERRUPT_VECTOR_COUNT. The
BSP_INTERRUPT_VECTOR_COUNT allows a default implementation which supports no
interrupt vector at all. Using COUNT instead of MAX may avoid some
interpretation issues, for example is the maximum value a valid vector number
or not.
Update #3269.
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Remove BSP_INTERRUPT_VECTOR_MIN and unconditionally let interrupt vector
numbers start with zero.
The BSP_INTERRUPT_VECTOR_MIN == 0 invariant was tested by the previous commit
and building all BSPs.
Update #3269.
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The a72 BSPs are identical to the a53 BSPs just changing a53 to a72.
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Currently, the AArch64 BSPs have a hard time running on real hardware
without building the toolchain and the bsps with -mstrict-align in
multiple places. Configuring the MMU on these chips allows for unaligned
memory accesses for non-device memory which avoids requiring strict
alignment in the toolchain and in the BSPs themselves.
In writing this driver, it was found that the synchronous exception
handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to
avoid thread stack misalignments in RTEMS_DEBUG mode. This is now
avoided by exactly preserving thread mode stack and flags and the new
implementation is compatible with the draft information provided on the
mailing list covering the Exception Management API.
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Ensure that cache functions are flagged as usable by the generic cache
implementation code.
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This fixes a bug where addresses were not being aligned correctly.
Addresses used in cache functions are now aligned consistently using
RTEMS_ALIGN_DOWN.
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Break out system register definitions and accessors so that they're
usable by other parts of RTEMS.
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Constantly reinitializing the Cadence UART on every character output
causes data corruption/loss on some ZynqMP hardware. Only initialize
the UART once for early output and give it a kick on startup.
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