| Commit message (Collapse) | Author | Age | Files | Lines |
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This test exercises the ability to obtain and modify
the affinity field of the POSIX thread attributes.
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This test exercises the new Classic API task affinity methods.
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This is a useful POSIX thread API helper which is found in
`GNU/Linux and *BSD.
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This patch adds the following methods:
+ pthread_get_affinity_np
+ pthread_set_affinity_np
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This patch adds the following methods:
+ pthread_attr_get_affinity_np
+ pthread_attr_set_affinity_np
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With the addition of pthread affinity information in pthread_attr_t,
the existing code for pthread_attr_t had to be adjusted.
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Add the following methods:
+ rtems_task_get_affinity
+ rtems_task_set_affinity
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SMP must be initialized in order to know the current set of
cores available. Without this, you cannot initialize the
default cpu_set_t associated with Classic API tasks and
POSIX threads.
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This new Score Handler provides a structure to manage a
cpu_set_t plus helper routines to validate the contents
against the current system configuration.
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If <sys/cpuset.h> is not provided by the toolset, the test
cannot be compiled.
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This function was only used in some tests and can be replaced with other
functions.
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Some _Context_Switch() invocations end up in _Thread_Handler(). Create
the right context for this function.
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A new option RTEMS_INTERRUPT_REPLACE is introduced that permits updating
the first interrupt handler for the registered interrupt vector and
matching argument. If no match is found, the install function fails
with RTEMS_UNSATISFIED.
The Interrupt Manager Extension offers interrupt handlers with an
argument pointer. It is impossible to update two words (handler and
argument) atomically on most architectures. In order to avoid an SMP
lock in bsp_interrupt_handler_dispatch() which would degrade the
interrupt response time an alternative must be provided that makes it
possible to tear-down interrupt sources without an SMP lock.
Add RTEMS_INTERRUPT_REPLACE option to Interrupt Manager Extension. This
enables a clean tear-down of interrupt sources on SMP configurations.
Instead of an interrupt handler removal a replacement handler can be
installed to silence an interrupt source. This can be used in contexts
that allow no sophisticated synchronization (e.g. in atexit() or fatal
handlers).
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New test smptests/smpfatal03.
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Rename _SMP_Request_other_cores_to_perform_first_context_switch() into
_SMP_Request_start_multitasking() since this requests now a multitasking
start on all configured and available processors. The name corresponds
_Thread_Start_multitasking() and
_SMP_Start_multitasking_on_secondary_processor() actions issued in
response to this request. Move in source file to right place.
Rename PER_CPU_STATE_READY_TO_BEGIN_MULTITASKING into
PER_CPU_STATE_READY_TO_START_MULTITASKING.
Rename PER_CPU_STATE_BEGIN_MULTITASKING into
PER_CPU_STATE_REQUEST_START_MULTITASKING.
Rename _SMP_Request_other_cores_to_shutdown() into
_SMP_Request_shutdown().
Add a per-CPU state lock to protect all changes. This was necessary to
offer a controlled shutdown of the system (atomic read/writes alone are
not sufficient for this kind of synchronization).
Add documentation for Per_CPU_State.
Delete debug output.
New tests smptests/smpfatal01 and smptests/smpfatal02.
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The previous implementation used an instruction cache line size of 0,
this is a bogus value. Use a instruction cache line size of 64 since
the L2 cache may have a line size of 32 or 64. A greater value should
cause no harm.
Use a FLUSH operation for _CPU_cache_invalidate_instruction_range().
This is a preperation step to support the L2 cache.
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Add rtems_cache_get_data_cache_size() and
rtems_cache_get_instruction_cache_size().
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A cache line cannot have a negative size.
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Move useful functions to the top of the file.
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The vector number of spurious interrupts was wrong after the interrupt
handler removal on SMP configurations.
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The SPARC processors supported by RTEMS have no built-in CPU counter
support. We have to use some hardware counter module for this purpose.
The BSP must provide a 32-bit register which contains the current CPU
counter value and a function for the difference calculation. It can use
for example the GPTIMER instance used for the clock driver.
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Do not use _TLS_Size here since this will lead GCC to assume that this
symbol is not 0 and the later > 0 test will be optimized away.
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Adjust test to work with clock driver based CPU counters. They have a
period equal to the clock tick interval.
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This is necessary to add tests that use the cache manager. For example
to get better estimates of worst-case timings.
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The 32-bit ABIs for thread-local storage (TLS) and EABI read-only
small-data area have a conflicting register (r2) usage. Use the System
V small-data instead (here r2 is system reserved).
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Remove RTEMS_COMPILER_PURE_ATTRIBUTE from _SMP_Get_current_processor()
and all _CPU_SMP_Get_current_processor(). Make inline ASM statements
volatile again. Test smptests/smpmigration01 showed that GCC optimizes
too much otherwise.
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Fix serious race-condition. Read the heir after the per-CPU lock
acquire.
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Rename _Internal_error_Occurred() into _Terminate().
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