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* bootstrap: Sort the various hash keys used in generating preinstall.am.Chris Johns2014-08-291-4/+4
| | | | | Something must have changed in perl to change the way the keys are ordered by default.
* Regenerate all preinstall.am files.Joel Sherrill2014-08-2895-464/+464
| | | | | Apparently, at some point automake output changed and these were not updated.
* arm: Add tests which fail to build with C++ enabled.Chris Johns2014-08-289-0/+24
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* preinstall: Regenerated files differ from the repo.Chris Johns2014-08-284-15/+18
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* virtex5/.../bsp.h: Add BSP_Convert_decrementer() macro required by MPC6xx ↵Joel Sherrill2014-08-271-3/+24
| | | | timer driver
* nds/Makefile.am: Rework to avoid creating ltos of .rel filesJoel Sherrill2014-08-271-71/+35
| | | | This was necessary to enable all tests to link.
* lpc40xx_ea_rom_int-testsuite.tcfg: New fileJoel Sherrill2014-08-271-0/+7
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* rtems: SMP fix for timer serverSebastian Huber2014-08-271-1/+3
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* arm/lm3s3749: Add tests that do not fit.Chris Johns2014-08-271-0/+3
| | | | You need --enable-c++ for the c++ tests.
* Add or1ksim (sim.cfg) configuration file and edit README.Hesham ALMatary2014-08-262-1/+123
| | | | | | | OpenRISC/or1ksim BSP: The new sim.cfg file configures or1ksim emulator with HW capabilities that the current RTEMS/or1ksim BSP supports. README: HOWTO run the or1ksim simulator.
* bsp/altera-cyclone-v: Add DMA support hwlib filesSebastian Huber2014-08-2617-7/+21297
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* bsp/altera-cyclone-v: Update to hwlib 13.1Sebastian Huber2014-08-2616-3841/+8786
| | | | This version is distributed with SoC EDS 14.0.0.200.
* rtems: Add more clock tick functionsSebastian Huber2014-08-265-0/+239
| | | | | Add rtems_clock_tick_later(), rtems_clock_tick_later_usec() and rtems_clock_tick_before().
* or1k/Makefile.am: libbsp_a_CPPFLAGS was defined twiceJoel Sherrill2014-08-251-1/+1
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* gensh4: Improve ROM vs RAM startup configurationJoel Sherrill2014-08-252-9/+16
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* gensh4/bsp_specs: Account for big/little endianJoel Sherrill2014-08-251-1/+1
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* simsh4-testsuite.tcfg: new fileJoel Sherrill2014-08-251-1/+5
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* simsh2e-testsuite.tcfg: new fileJoel Sherrill2014-08-251-1/+5
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* shsim/bsp_specs: Account for big/little endianJoel Sherrill2014-08-251-1/+1
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* or1ksim BSP: Include cache manager stubs, and re-generate preinstall.am files.Hesham ALMatary2014-08-253-36/+46
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* Add or1k to the list of targets that use IEEE 754 in xdr_float.cHesham ALMatary2014-08-251-0/+1
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* Rename or1k_or1ksim BSP to or1ksimHesham ALMatary2014-08-251-0/+0
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* libcpu: Add new entry for or1k cpu and include cache manager stubs.Hesham ALMatary2014-08-254-0/+85
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* sptests/spcache01: Make inline assembly conditional to account for OpenRISC ↵Hesham ALMatary2014-08-251-1/+5
| | | | l.nop instruction.
* bsp/mpc55xx: Fix commentSebastian Huber2014-08-251-1/+1
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* bsp/mpc55xx: Add defines for MPC5668Sebastian Huber2014-08-252-7/+13
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* bsp/mpc55xx: Limit flash support to MPC55[56]XSebastian Huber2014-08-251-1/+1
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* rtems: Inline rtems_clock_get_ticks_since_boot()Sebastian Huber2014-08-256-68/+24
| | | | Update documentation.
* score: Add missing define to cache managerDaniel Cederman2014-08-251-0/+2
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* bsp/tms570: implemented and tested initialization of Cortex-R performance ↵Pavel Pisa2014-08-221-4/+84
| | | | | | | | | | | | counters. The code is written as BSP specific now but it should work for all Cortex-A and R based CPUs and can be moved to ARM generic place in future. StackOverflow suggested sequences of writes to the registers required to start counters is used. http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor
* smptests/smpcache01: Test the SMP cache managerDaniel Cederman2014-08-226-0/+342
| | | | Invokes SMP cache management routines under different scenarios.
* score: Add SMP support to the cache managerDaniel Cederman2014-08-224-6/+355
| | | | | | | | | Adds functions that allows the user to specify which cores that should perform the cache operation. SMP messages are sent to all the specified cores and the caller waits until all cores have acknowledged that they have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is defined the instruction cache invalidation function will perform the operation on all cores using the previous method.
* bsp/sparc: Flush only instruction cacheDaniel Cederman2014-08-222-1/+9
| | | | | | The flush instruction on LEON flushes both the data and the instruction cache. Flushing of just the instruction cache can be done by setting the "flush instruction cache" bit in the cache control register.
* score/sparc: Add comment on icache flush after trap table updateDaniel Cederman2014-08-221-3/+14
| | | | | | | | | | | Changes to the trap table might be missed by other cores. If the system state is up, the other cores can be notified using SMP messages that they need to flush their icache. If the up state has not been reached there is no need to notify other cores. They will do an automatic flush of the icache just after entering the up state, but before enabling interrupts. Cache invalidation is required for both single and multiprocessor systems.
* bsp/sparc: Flush icache before first time enabling interruptsDaniel Cederman2014-08-222-0/+13
| | | | | | | A secondary processor might miss changes done to the trap table if the instruction cache is not flushed. Once interrupts are enabled any other required cache flushes can be ordered via the cache manager.
* score: Rename SMP broadcast message functionDaniel Cederman2014-08-222-3/+3
| | | | Change message type to unsigned long to match other SMP message functions.
* score: Add function to send a SMP message to a set of CPUsDaniel Cederman2014-08-222-0/+31
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* libchip/dwmac: Make PHY address user configurableChristian Mauderer2014-08-224-12/+58
| | | | | | This patch allows the user to configure the PHY address for the DWMAC driver by giving a pointer to a dwmac_user_cfg structure to network stack via rtems_bsdnet_ifconfig::drv_ctrl.
* bsp/tms570: disable huge memory demanding tests for internal RAM build variant.Pavel Pisa2014-08-212-13/+23
| | | | | | | | | | | | | BSP completes build with tests and debug enabled for all three variants now tms570ls3137_hdk tms570ls3137_hdk_intram tms570ls3137_hdk_sdram Even that all enabled tests builds for internal RAM variant, many of them are expected to fail on hardware because whole tests including code, data and runtime work area demands has to fit into 256 kB of RAM.
* bsp/tms570: implemented support functions to satisfy complete tests build ↵Pavel Pisa2014-08-219-4/+186
| | | | | | | | requirements. This patch enables to build all RTEMS tests for tms570ls3137_hdk_sdram BSP variant in in default build. Debug build with --enable-rtems-debug set has succeed for samples subset of tests as well.
* Add configuration to detect toolset has sigaltstack() prototypeJoel Sherrill2014-08-202-4/+18
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* mpc55xx/misc/flash_support.c: Properly flush cache when writing.Peter Dufault2014-08-201-46/+39
| | | | | | | Also cleanup: * Remove un-needed interrupt disables. * Address errata "e989: FLASH: Disable Prefetch during programming and erase" * Use RTEMS_ARRAY_SIZE() macro instead of own macro.
* or1k.t: Fix spelling errorsJoel Sherrill2014-08-201-4/+4
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* Add new documentation section for OpenRISC CPU architecture.Hesham ALMatary2014-08-203-0/+84
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* libbsp/arm/acinclude.m4: Regenerate for tms570Joel Sherrill2014-08-201-0/+2
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* Add new (first) OpenRISC BSP called or1ksim.Hesham ALMatary2014-08-2024-0/+1610
| | | | | This BSP is intended to run on or1ksim (the main OpenRISC emulator). Fixed version according to Joel comments from the mailing list.
* BSP for TMS570LS31x Hercules Development Kit from TI (TMS570LS3137)Premysl Houdek2014-08-2028-0/+2389
| | | | | | | | | | | | | | | | | | | | | | | | | Included variants: tms570ls3137_hdk_intram - place code and data into internal SRAM tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM tms570ls3137_hdk - variant prepared for stand-alone RTEMS aplication stored and running directly from flash. Not working yet. Chip initialization code not included in BSP. External startup generated by TI's HalCoGen was used for testing and debugging. More information about TMS570 BSP can be found at http://www.rtems.org/wiki/index.php/Tms570 Patch version 2 - most of the formatting suggestion applied. - BSP converted to use clock shell - console driver "set attributes" tested. Baudrate change working Patch version 3 - more formatting changes. - removed leftover defines and test functions Todo: refactor header files (name register fields)
* lpc24xx/lpc17xx: lpc24xx_pin_set_function() keep LPC4088 W type pin in ↵Pavel Pisa2014-08-201-1/+6
| | | | | | | | | | | | | | | | | | | | digital mode for non-analog function. The problem wit incorrect switching of pins into analog mode manifestes on LPC4088 based board. LPC4088 implements pin P1.17 (ENET_MDIO) as new W type (digital pin with analog option). The pin was listed as D category on LPC1788 which does not have analog mode control bit. If analog option is not explicitly switched off on LPC4088 then the pin does not work as digital pin. Code tested on LPC1788 and no problems has been observed even that manual specifies the IOCON_ADMODE field as reserved and should be written as zero. But even RTEMS lpc24xx_gpio_config sets this bit unconditionally. Signed-off-by: Pavel Pisa <ppisa@pikron.com>
* score: PR2179: Fix initially locked PI mutexSebastian Huber2014-08-203-4/+50
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* rtems_termios_puts: Copy and write more than one char at onceKolja Waschk2014-08-181-50/+85
| | | | Renamed startXmit(), nToSend is unsigned, just check FL_ORCVXOF, no (void) cast anymore, compute nToSend in single if/else if/else.
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