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* csb337/.../bspreset.c: Eliminate warning for set not used variableJoel Sherrill2014-09-041-1/+0
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* raspberrypi: Use shared bspreset.cJoel Sherrill2014-09-044-69/+34
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* libfs: Fix the warning in the RFS.Chris Johns2014-09-031-1/+6
| | | | Return the first error if one or more happen when deleting an inode.
* or1ksim/Makefile.am: Install shared tm27.h and regenerate preinstall.amJoel Sherrill2014-09-022-5/+5
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* or1k: Implement context validate and context volatile clobber functions.Hesham ALMatary2014-09-024-3/+225
| | | | | | score/cpu/or1k: Add two new assembly functions: _CPU_Context_validate and _CPU_Context_volatile_clobber; their implementation follows corresponding ARM functions.
* Add missing r31 load instruction _ISR_HandlerHesham ALMatary2014-09-021-0/+1
| | | | | _ISR_Handler: r31 was not loaded in restore function. This patch adds this load.
* sapi: Add profiling report begin/end messageSebastian Huber2014-09-021-3/+7
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* samples/iostream: Produce proper begin/end messageSebastian Huber2014-09-012-4/+4
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* smptests/smplock01: Update screen fileSebastian Huber2014-09-011-1/+1
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* libtests/capture01: Fix test nameSebastian Huber2014-09-011-1/+1
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* libtests/capture01: Force error if SMP enabledSebastian Huber2014-09-011-0/+5
| | | | | This prevents infinite test runs on SMP due to the recursive interrupt lock acquire.
* tests: Add documentationSebastian Huber2014-09-0112-17/+97
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* smptests/smpfatal08: Fix link errorSebastian Huber2014-09-011-0/+7
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* score: Define _CPU_Start_multitasking only for LEON SPARC, not SPARC in generalDaniel Cederman2014-09-012-3/+5
| | | | | Rename _BSP_Start_multitasking to _LEON3_Start_multitasking to show that it is LEON specific
* bsp/ngmp: Use -mcpu=leon3 GCC optionSebastian Huber2014-09-011-0/+2
| | | | | | | | | | | | | | | | | | There is support for the LEON3 processor available in Binutils 2.24 and the GCC 4.8 branch and GCC mainline. GCC 4.8 branch: http://gcc.gnu.org/viewcvs/gcc/branches/?view=log&pathrev=205331 GCC mainline: http://gcc.gnu.org/viewcvs/gcc/trunk/?view=log&pathrev=202664 It is mandatory to use this option for SMP on LEON3 since it enables usage of C11 atomic operations. It makes it also possible to use an inline function for _CPU_SMP_Get_current_processor() which avoids the function call overhead in critical sections.
* Regenerate all preinstall.am files.Chris Johns2014-08-29101-447/+447
| | | | | With this patch the preinstall.am files are in a set order and not dependent on now perl implements a hash.
* bootstrap: Sort the various hash keys used in generating preinstall.am.Chris Johns2014-08-291-4/+4
| | | | | Something must have changed in perl to change the way the keys are ordered by default.
* Regenerate all preinstall.am files.Joel Sherrill2014-08-2895-464/+464
| | | | | Apparently, at some point automake output changed and these were not updated.
* arm: Add tests which fail to build with C++ enabled.Chris Johns2014-08-289-0/+24
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* preinstall: Regenerated files differ from the repo.Chris Johns2014-08-284-15/+18
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* virtex5/.../bsp.h: Add BSP_Convert_decrementer() macro required by MPC6xx ↵Joel Sherrill2014-08-271-3/+24
| | | | timer driver
* nds/Makefile.am: Rework to avoid creating ltos of .rel filesJoel Sherrill2014-08-271-71/+35
| | | | This was necessary to enable all tests to link.
* lpc40xx_ea_rom_int-testsuite.tcfg: New fileJoel Sherrill2014-08-271-0/+7
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* rtems: SMP fix for timer serverSebastian Huber2014-08-271-1/+3
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* arm/lm3s3749: Add tests that do not fit.Chris Johns2014-08-271-0/+3
| | | | You need --enable-c++ for the c++ tests.
* Add or1ksim (sim.cfg) configuration file and edit README.Hesham ALMatary2014-08-262-1/+123
| | | | | | | OpenRISC/or1ksim BSP: The new sim.cfg file configures or1ksim emulator with HW capabilities that the current RTEMS/or1ksim BSP supports. README: HOWTO run the or1ksim simulator.
* bsp/altera-cyclone-v: Add DMA support hwlib filesSebastian Huber2014-08-2617-7/+21297
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* bsp/altera-cyclone-v: Update to hwlib 13.1Sebastian Huber2014-08-2616-3841/+8786
| | | | This version is distributed with SoC EDS 14.0.0.200.
* rtems: Add more clock tick functionsSebastian Huber2014-08-265-0/+239
| | | | | Add rtems_clock_tick_later(), rtems_clock_tick_later_usec() and rtems_clock_tick_before().
* or1k/Makefile.am: libbsp_a_CPPFLAGS was defined twiceJoel Sherrill2014-08-251-1/+1
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* gensh4: Improve ROM vs RAM startup configurationJoel Sherrill2014-08-252-9/+16
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* gensh4/bsp_specs: Account for big/little endianJoel Sherrill2014-08-251-1/+1
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* simsh4-testsuite.tcfg: new fileJoel Sherrill2014-08-251-1/+5
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* simsh2e-testsuite.tcfg: new fileJoel Sherrill2014-08-251-1/+5
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* shsim/bsp_specs: Account for big/little endianJoel Sherrill2014-08-251-1/+1
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* or1ksim BSP: Include cache manager stubs, and re-generate preinstall.am files.Hesham ALMatary2014-08-253-36/+46
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* Add or1k to the list of targets that use IEEE 754 in xdr_float.cHesham ALMatary2014-08-251-0/+1
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* Rename or1k_or1ksim BSP to or1ksimHesham ALMatary2014-08-251-0/+0
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* libcpu: Add new entry for or1k cpu and include cache manager stubs.Hesham ALMatary2014-08-254-0/+85
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* sptests/spcache01: Make inline assembly conditional to account for OpenRISC ↵Hesham ALMatary2014-08-251-1/+5
| | | | l.nop instruction.
* bsp/mpc55xx: Fix commentSebastian Huber2014-08-251-1/+1
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* bsp/mpc55xx: Add defines for MPC5668Sebastian Huber2014-08-252-7/+13
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* bsp/mpc55xx: Limit flash support to MPC55[56]XSebastian Huber2014-08-251-1/+1
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* rtems: Inline rtems_clock_get_ticks_since_boot()Sebastian Huber2014-08-256-68/+24
| | | | Update documentation.
* score: Add missing define to cache managerDaniel Cederman2014-08-251-0/+2
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* bsp/tms570: implemented and tested initialization of Cortex-R performance ↵Pavel Pisa2014-08-221-4/+84
| | | | | | | | | | | | counters. The code is written as BSP specific now but it should work for all Cortex-A and R based CPUs and can be moved to ARM generic place in future. StackOverflow suggested sequences of writes to the registers required to start counters is used. http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor
* smptests/smpcache01: Test the SMP cache managerDaniel Cederman2014-08-226-0/+342
| | | | Invokes SMP cache management routines under different scenarios.
* score: Add SMP support to the cache managerDaniel Cederman2014-08-224-6/+355
| | | | | | | | | Adds functions that allows the user to specify which cores that should perform the cache operation. SMP messages are sent to all the specified cores and the caller waits until all cores have acknowledged that they have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is defined the instruction cache invalidation function will perform the operation on all cores using the previous method.
* bsp/sparc: Flush only instruction cacheDaniel Cederman2014-08-222-1/+9
| | | | | | The flush instruction on LEON flushes both the data and the instruction cache. Flushing of just the instruction cache can be done by setting the "flush instruction cache" bit in the cache control register.
* score/sparc: Add comment on icache flush after trap table updateDaniel Cederman2014-08-221-3/+14
| | | | | | | | | | | Changes to the trap table might be missed by other cores. If the system state is up, the other cores can be notified using SMP messages that they need to flush their icache. If the up state has not been reached there is no need to notify other cores. They will do an automatic flush of the icache just after entering the up state, but before enabling interrupts. Cache invalidation is required for both single and multiprocessor systems.
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