| Commit message (Collapse) | Author | Age | Files | Lines |
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Close #3720.
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The register definition for the CP15 PMCR (performance monitor control
register) has the bits for X (export enable) and D (clock divider
enable) backwards. Correct them according to ARMv7-A/R Architecture
Reference Manual, Rev C, Section B4.1.117.
Consequences: On an implementation that starts off with D set at reset,
the clock divider will not be disabled by using RTEMS' definition of the
D bit.
Tested by using the counter on Xilinx Zynq 7020 to measure some atomic
accesses and cache flushing operations.
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They are only used by this BSP.
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Updates #3687
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- Add a small memory test config file.
- Update the small memory PowerPC BSPs to use the new test config.
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For proper 16 bits per word support we need probably some DMA
adjustments. For 9 to 15 bits per word we need support for the variable
peripheral select, see SR_MR[PS] register bit.
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Load the channel interrupt mask only once.
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The previous approach contained a severe bug which disabled the SPI
module in some cases leading to a blocked SPI bus.
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Do not use SPID_Configure() since this will enable the peripheral each
time and performs a software reset.
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They are only used by PowerPC BSPs.
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Move the .rtemsstack section from a read-only to a read-write area, see
page table setup in __BSP_default_pgtbl_setup().
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Previous warning fixes which include <sys/param.h> broke this macro.
The definition of PAGE_MASK changed.
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Update #3707.
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Update #3706
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- Use CamelCase as it is not used in our C code. Enables simple search and
replace.
- Prefix with "RTEMS" to aid deployment and integration. It aids
searching and sorting.
Update #3706.
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Generate Doxygen output in doc and ignore this directory in Git. Add
RTEMS logo. The Doxygen documentation is now built using the source
tree. Just invoke "doxygen" in the top-level source directory.
The Doxyfile works also with at least Doxygen 1.8.13 and Doxygen 1.8.14.
Update #3705.
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Update #3705.
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Remove the priority node only in case it is active.
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The following variants
* GICv1 with Security Extensions,
* GICv2 without Security Extensions, or
* within Secure processor mode
have the ability to assign group 0 or 1 to individual interrupts. Group
0 interrupts can be configured to raise an FIQ exception. This enables
the use of NMIs with respect to RTEMS.
BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
define. Use arm_gic_irq_set_group() to change the group of an
interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is
defined).
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This makes the @file documentation independent of the actual file name.
Update #3707.
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This gets rid of a special include path.
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The system register in use for retrieval of the virtual timer value was
mistakenly copied from the physical timer value retrieval function.
Virtual timer value retrieval should use the same system register as the
virtual timer value setter.
Close #3699.
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Coverity 1399717
Updates #3686
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Coverty 1442636
Updates #3686
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space.
Coverity issue 1442540
Updates #3686
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Coverity issue 1442641
Updates #3686
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- Allow an allocator to lock the allocations. This is needed to
lock the heap allocator so the text and trampoline table are
as close together as possible to allow for the largest possible
object file size.
- Update the default heap allocator to lock the heap allocator.
- Update ELF loading to lock the allocator.
Updates #3685
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Move device tree copy operation after the mode initialization so that
bsp_fdt_copy() uses the initialization stack and not the stack provided
up by the boot loader.
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Update #3334.
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Recursive usage of the same pthread_once_t results now in a deadlock.
Previously, an error of EINVAL was returned. This usage scenario is
invalid according to the POSIX pthread_once() specification.
Close #3334.
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Updates #3687
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Close #3692
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This file is unused and makes trouble on Windows.
Updates #3638.
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Fix small data area in case no fixed size is desired. Rename
bsp_section_set_sdata_sbss_size into bsp_section_small_data_area_size
since this symbol reflects the overall small data area size (including
space for libdl). Do not use bsp_section_sbss_size before definition in
linker command file. Add new symbols to <bsp/linker-symbols.h>.
Update #3687.
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- Add support for architecure sections that can be handled by the
architecture back end.
- Add trampoline/fixup support for PowerPC. This means the PowerPC
now supports large memory loading of applications.
- Add a bit allocator to manage small block based regions of memory.
- Add small data (sdata/sbss) support for the PowerPC. The support
makes the linker allocated small data region of memory a global
resource available to libdl loaded object files.
Updates #3687
Updates #3685
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