| Commit message (Collapse) | Author | Age | Files | Lines |
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Update #3269.
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Bring the error conditions and status in line with
rtems_task_get_affinity() and rtems_task_set_affinity().
Update #3269.
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Update #3269.
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The LDFLAGS are placed after the static libraries in the standard waf link
command, see "waflib/Tools/c.py" in the waf sources.
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The heap protection is conditional.
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BSP family and BSP variant names may be equal. This prefix avoids
ambiguity in the enabled-by expressions.
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When compiling the lwIP port for the TMS570, there
were issues with the BSP. Headers are expected in a folder
named ti_herc which did not exist. This fixes the issue.
Furthermore, there were multiple warnings about define redefinitions.
This was fixed as well.
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These patches were submitted a few months ago, but it was found out
that the default-by-family: [] were missing in the GPIO .yml lines.
This was fixed in this patch.
This patch accounts for different pins for the ETH peripheral
on STM32H7 devices. For example, the Nucleo H743ZI has slightly
different pins than other STM32H7 boards.
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The <leon.h> header file contains a lot of implementation details. Hide them
from <bsp.h>.
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Prefer RTEMS_FATAL_SOURCE_EXCEPTION over
INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT since the fatal code
(rtems_exception_frame) provides more context.
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This makes it possible to use the BSP family in expressions of the enabled-by
attribute.
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Update #4468.
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Update #4468.
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Update #4468.
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This program contained an optional test case. It was enabled by the
RTEMS_COVERAGE define. The functions under test are not implemented by RTEMS.
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- Optionally add support for 'default-by-family' to allow
option to be set by a family and so all related BSPs
Close #4468
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Fully support the interrupt extension API to set/get the interrupt affinity.
Remove LEON3_irq_to_cpu which defined the interrupt to processor mapping in a
BSP-specific way.
Update #3269.
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Flush imx_gic_dist_base so that secondary processors can use the right
address.
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Skip the data cache initialization if we are a secondary processor.
The bug was introduced by e164df5e33608576443b4cd5923a9046358ee773 and
did not show up in tests using Qemu since the data cache behaviour is
not emulated.
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Update smpstrongapa01 to account for task shifting.
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Calling the memory FLASH and EXTRAM instead of FLEXSPI and SDRAM makes
it simpler to support other types of external RAM. This patch also
removes some of the calculations and improves names and documentation to
avoid pitfalls. It removes a unnecessary memory definition.
Update #4180
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Update #4180
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Fixes a problem with bad epilog code in _fini and to keep sections
necessary with the -ffunction/data-sections.
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This reverts commit 10041a4cfc00d5f6876d3d6cfc30c23347b4cf42.
This type of configuration does not belong in RTEMS and is better
constrained to libbsd where the defines are actually being used.
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This function is not performance critical. There is no need to
implement it inline.
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The fix to address CID 1399742 (NO_EFFECT) in commit
f8b6359415404540864f809cbcffb8c2200261e1 introduced a bug since
LEON3_IrqCtrl_EIrq == -1 in case no extended interrupts are supported by
the interrupt controller. Fix this by checking for
LEON3_IrqCtrl_EIrq > 0.
In addition, interrupt number 0 is reserved and should not be used.
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Close #4463.
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The GICv3 support is shared between AArch32 and AArch64. For AArch32,
the new AARCH64_IS_NONSECURE is never defined. Use ARM_MULTILIB_ARCH_V4
instead.
This issue was introduced by 76c6caad52244ab9a14151620a80ff0f71035b6c.
There is still a change in bsp_interrupt_vector_enable() for AArch32
compared to the version before 76c6caad52244ab9a14151620a80ff0f71035b6c.
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Move the moduleid register to the correct offset according to Cadence IP
documentation.
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The existing fix for the ZynqMP UART hardware bug only caught the vast
majority of instances where it could occur. To fully fix the data
corruption, this fix must be applied after every baud rate change. This
makes the logic reset and kick apply in any locations where the baud
rate could be changed.
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The Cortex-R52 does not support cache coherency and the shareable memory
attribute. If a region is configured to be shareable, then it falls
back to use non-cacheable memory.
Update #4202.
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Update #4202.
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Update #4202.
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Disable the alignment check through SCTLR[A] in
_AArch32_PMSA_Initialize().
Update #4202.
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Provide the options necessary to enable any combination of CGEM ethernet
interfaces in LibBSD. The default is still CGEM3, so this should
continue to operate as expected on typical Zynq Ultrascale+ MPSoC
development hardware.
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