diff options
Diffstat (limited to 'testsuites/validation/tc-intr-vector-enable.c')
-rw-r--r-- | testsuites/validation/tc-intr-vector-enable.c | 65 |
1 files changed, 42 insertions, 23 deletions
diff --git a/testsuites/validation/tc-intr-vector-enable.c b/testsuites/validation/tc-intr-vector-enable.c index c0d985a9d0..91993fb8d4 100644 --- a/testsuites/validation/tc-intr-vector-enable.c +++ b/testsuites/validation/tc-intr-vector-enable.c @@ -3,11 +3,11 @@ /** * @file * - * @ingroup RTEMSTestCaseRtemsIntrReqVectorEnable + * @ingroup RtemsIntrReqVectorEnable */ /* - * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2021 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -61,10 +61,9 @@ #include <rtems/test.h> /** - * @defgroup RTEMSTestCaseRtemsIntrReqVectorEnable \ - * spec:/rtems/intr/req/vector-enable + * @defgroup RtemsIntrReqVectorEnable spec:/rtems/intr/req/vector-enable * - * @ingroup RTEMSTestSuiteTestsuitesValidation0 + * @ingroup TestsuitesValidationIntr * * @{ */ @@ -139,6 +138,12 @@ typedef struct { struct { /** + * @brief This member defines the pre-condition indices for the next + * action. + */ + size_t pci[ 3 ]; + + /** * @brief This member defines the pre-condition states for the next action. */ size_t pcs[ 3 ]; @@ -362,7 +367,7 @@ static void RtemsIntrReqVectorEnable_Pre_IsEnabled_Prepare( case RtemsIntrReqVectorEnable_Pre_IsEnabled_No: { /* * While the interrupt vector associated with the ``vector`` parameter is - * enabled. + * disabled. */ /* * This pre-condition depends on the attributes of an interrupt vector, @@ -600,19 +605,32 @@ static inline RtemsIntrReqVectorEnable_Entry RtemsIntrReqVectorEnable_PopEntry( ]; } +static void RtemsIntrReqVectorEnable_SetPreConditionStates( + RtemsIntrReqVectorEnable_Context *ctx +) +{ + ctx->Map.pcs[ 0 ] = ctx->Map.pci[ 0 ]; + + if ( ctx->Map.entry.Pre_IsEnabled_NA ) { + ctx->Map.pcs[ 1 ] = RtemsIntrReqVectorEnable_Pre_IsEnabled_NA; + } else { + ctx->Map.pcs[ 1 ] = ctx->Map.pci[ 1 ]; + } + + if ( ctx->Map.entry.Pre_CanEnable_NA ) { + ctx->Map.pcs[ 2 ] = RtemsIntrReqVectorEnable_Pre_CanEnable_NA; + } else { + ctx->Map.pcs[ 2 ] = ctx->Map.pci[ 2 ]; + } +} + static void RtemsIntrReqVectorEnable_TestVariant( RtemsIntrReqVectorEnable_Context *ctx ) { RtemsIntrReqVectorEnable_Pre_Vector_Prepare( ctx, ctx->Map.pcs[ 0 ] ); - RtemsIntrReqVectorEnable_Pre_IsEnabled_Prepare( - ctx, - ctx->Map.entry.Pre_IsEnabled_NA ? RtemsIntrReqVectorEnable_Pre_IsEnabled_NA : ctx->Map.pcs[ 1 ] - ); - RtemsIntrReqVectorEnable_Pre_CanEnable_Prepare( - ctx, - ctx->Map.entry.Pre_CanEnable_NA ? RtemsIntrReqVectorEnable_Pre_CanEnable_NA : ctx->Map.pcs[ 2 ] - ); + RtemsIntrReqVectorEnable_Pre_IsEnabled_Prepare( ctx, ctx->Map.pcs[ 1 ] ); + RtemsIntrReqVectorEnable_Pre_CanEnable_Prepare( ctx, ctx->Map.pcs[ 2 ] ); RtemsIntrReqVectorEnable_Action( ctx ); RtemsIntrReqVectorEnable_Post_Status_Check( ctx, @@ -639,21 +657,22 @@ T_TEST_CASE_FIXTURE( ctx->Map.index = 0; for ( - ctx->Map.pcs[ 0 ] = RtemsIntrReqVectorEnable_Pre_Vector_Valid; - ctx->Map.pcs[ 0 ] < RtemsIntrReqVectorEnable_Pre_Vector_NA; - ++ctx->Map.pcs[ 0 ] + ctx->Map.pci[ 0 ] = RtemsIntrReqVectorEnable_Pre_Vector_Valid; + ctx->Map.pci[ 0 ] < RtemsIntrReqVectorEnable_Pre_Vector_NA; + ++ctx->Map.pci[ 0 ] ) { for ( - ctx->Map.pcs[ 1 ] = RtemsIntrReqVectorEnable_Pre_IsEnabled_Yes; - ctx->Map.pcs[ 1 ] < RtemsIntrReqVectorEnable_Pre_IsEnabled_NA; - ++ctx->Map.pcs[ 1 ] + ctx->Map.pci[ 1 ] = RtemsIntrReqVectorEnable_Pre_IsEnabled_Yes; + ctx->Map.pci[ 1 ] < RtemsIntrReqVectorEnable_Pre_IsEnabled_NA; + ++ctx->Map.pci[ 1 ] ) { for ( - ctx->Map.pcs[ 2 ] = RtemsIntrReqVectorEnable_Pre_CanEnable_Yes; - ctx->Map.pcs[ 2 ] < RtemsIntrReqVectorEnable_Pre_CanEnable_NA; - ++ctx->Map.pcs[ 2 ] + ctx->Map.pci[ 2 ] = RtemsIntrReqVectorEnable_Pre_CanEnable_Yes; + ctx->Map.pci[ 2 ] < RtemsIntrReqVectorEnable_Pre_CanEnable_NA; + ++ctx->Map.pci[ 2 ] ) { ctx->Map.entry = RtemsIntrReqVectorEnable_PopEntry( ctx ); + RtemsIntrReqVectorEnable_SetPreConditionStates( ctx ); RtemsIntrReqVectorEnable_TestVariant( ctx ); } } |