diff options
Diffstat (limited to 'spec/build/bsps/riscv/riscv')
29 files changed, 145 insertions, 192 deletions
diff --git a/spec/build/bsps/riscv/riscv/abi.yml b/spec/build/bsps/riscv/riscv/abi.yml index 58aaa861e4..bca6512f20 100644 --- a/spec/build/bsps/riscv/riscv/abi.yml +++ b/spec/build/bsps/riscv/riscv/abi.yml @@ -5,73 +5,54 @@ actions: - env-append: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG default: -- -march=rv32imac -- -mabi=ilp32 -default-by-family: [] -default-by-variant: -- value: +- enabled-by: + - riscv/mpfs64imafdc + - riscv/rv64imafdc + - riscv/kendrytek210 + value: - -march=rv64imafdc - -mabi=lp64d - -mcmodel=medany - variants: - - riscv/rv64imafdc_medany -- value: - - -march=rv64imafdc - - -mabi=lp64d - variants: - - riscv/rv64imafdc -- value: +- enabled-by: + - riscv/rv64imafd + - riscv/rv64imafd + value: - -march=rv64imafd - -mabi=lp64d - -mcmodel=medany - variants: - - riscv/rv64imafd_medany -- value: - - -march=rv64imafd - - -mabi=lp64d - variants: - - riscv/rv64imafd -- value: +- enabled-by: riscv/rv64imac + value: - -march=rv64imac - -mabi=lp64 - -mcmodel=medany - variants: - - riscv/rv64imac_medany -- value: - - -march=rv64imac - - -mabi=lp64 - variants: - - riscv/rv64imac -- value: [] - variants: - - riscv/rv32imafdc -- value: +- enabled-by: riscv/rv32imafdc + value: [] +- enabled-by: riscv/rv32imafd + value: - -march=rv32imafd - -mabi=ilp32d - variants: - - riscv/rv32imafd -- value: +- enabled-by: riscv/rv32imafc + value: - -march=rv32imafc - -mabi=ilp32f - variants: - - riscv/rv32imafc -- value: +- enabled-by: riscv/rv32im + value: - -march=rv32im - -mabi=ilp32 - variants: - - riscv/rv32im -- value: +- enabled-by: riscv/rv32iac + value: - -march=rv32iac - -mabi=ilp32 - variants: - - riscv/rv32iac -- value: +- enabled-by: riscv/rv32i + value: - -march=rv32i - -mabi=ilp32 - variants: - - riscv/rv32i +- enabled-by: true + value: + - -march=rv32imac + - -mabi=ilp32 description: | ABI flags enabled-by: true diff --git a/spec/build/bsps/riscv/riscv/bspfrdme310arty.yml b/spec/build/bsps/riscv/riscv/bspfrdme310arty.yml index a13b12dc3c..26c3b97dac 100644 --- a/spec/build/bsps/riscv/riscv/bspfrdme310arty.yml +++ b/spec/build/bsps/riscv/riscv/bspfrdme310arty.yml @@ -4,7 +4,7 @@ bsp: frdme310arty build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv64imacmedany.yml b/spec/build/bsps/riscv/riscv/bspkendrtyek210.yml index c0db3e0720..91c601979e 100644 --- a/spec/build/bsps/riscv/riscv/bsprv64imacmedany.yml +++ b/spec/build/bsps/riscv/riscv/bspkendrtyek210.yml @@ -1,10 +1,10 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause arch: riscv -bsp: rv64imac_medany +bsp: kendrytek210 build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2022 Alan Cudmore cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv64imafdmedany.yml b/spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml index 9e01572c70..4e0e7d227e 100644 --- a/spec/build/bsps/riscv/riscv/bsprv64imafdmedany.yml +++ b/spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml @@ -1,10 +1,10 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause arch: riscv -bsp: rv64imafd_medany +bsp: mpfs64imafdc build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv32i.yml b/spec/build/bsps/riscv/riscv/bsprv32i.yml index 168839eb31..8c35a4abaa 100644 --- a/spec/build/bsps/riscv/riscv/bsprv32i.yml +++ b/spec/build/bsps/riscv/riscv/bsprv32i.yml @@ -4,7 +4,7 @@ bsp: rv32i build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv32iac.yml b/spec/build/bsps/riscv/riscv/bsprv32iac.yml index ce226c6344..7468984cc9 100644 --- a/spec/build/bsps/riscv/riscv/bsprv32iac.yml +++ b/spec/build/bsps/riscv/riscv/bsprv32iac.yml @@ -4,7 +4,7 @@ bsp: rv32iac build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv32im.yml b/spec/build/bsps/riscv/riscv/bsprv32im.yml index a6c77b421b..a7dab33e94 100644 --- a/spec/build/bsps/riscv/riscv/bsprv32im.yml +++ b/spec/build/bsps/riscv/riscv/bsprv32im.yml @@ -4,7 +4,7 @@ bsp: rv32im build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv32imac.yml b/spec/build/bsps/riscv/riscv/bsprv32imac.yml index 25b9a4d00f..b9a684ba44 100644 --- a/spec/build/bsps/riscv/riscv/bsprv32imac.yml +++ b/spec/build/bsps/riscv/riscv/bsprv32imac.yml @@ -4,7 +4,7 @@ bsp: rv32imac build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv32imafc.yml b/spec/build/bsps/riscv/riscv/bsprv32imafc.yml index fa8ce6a1d1..fd8456afba 100644 --- a/spec/build/bsps/riscv/riscv/bsprv32imafc.yml +++ b/spec/build/bsps/riscv/riscv/bsprv32imafc.yml @@ -4,7 +4,7 @@ bsp: rv32imafc build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv32imafd.yml b/spec/build/bsps/riscv/riscv/bsprv32imafd.yml index 5ac45fdd2c..19d9d72144 100644 --- a/spec/build/bsps/riscv/riscv/bsprv32imafd.yml +++ b/spec/build/bsps/riscv/riscv/bsprv32imafd.yml @@ -4,7 +4,7 @@ bsp: rv32imafd build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv32imafdc.yml b/spec/build/bsps/riscv/riscv/bsprv32imafdc.yml index 104a7a1391..d6e2a0bb98 100644 --- a/spec/build/bsps/riscv/riscv/bsprv32imafdc.yml +++ b/spec/build/bsps/riscv/riscv/bsprv32imafdc.yml @@ -4,7 +4,7 @@ bsp: rv32imafdc build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv64imac.yml b/spec/build/bsps/riscv/riscv/bsprv64imac.yml index 99dab47754..7c539e18dd 100644 --- a/spec/build/bsps/riscv/riscv/bsprv64imac.yml +++ b/spec/build/bsps/riscv/riscv/bsprv64imac.yml @@ -4,7 +4,7 @@ bsp: rv64imac build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv64imafd.yml b/spec/build/bsps/riscv/riscv/bsprv64imafd.yml index 730a76a41d..23fd0ae350 100644 --- a/spec/build/bsps/riscv/riscv/bsprv64imafd.yml +++ b/spec/build/bsps/riscv/riscv/bsprv64imafd.yml @@ -4,7 +4,7 @@ bsp: rv64imafd build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv64imafdc.yml b/spec/build/bsps/riscv/riscv/bsprv64imafdc.yml index 32a0837941..017cad67fa 100644 --- a/spec/build/bsps/riscv/riscv/bsprv64imafdc.yml +++ b/spec/build/bsps/riscv/riscv/bsprv64imafdc.yml @@ -4,7 +4,7 @@ bsp: rv64imafdc build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: riscv diff --git a/spec/build/bsps/riscv/riscv/bsprv64imafdcmedany.yml b/spec/build/bsps/riscv/riscv/bsprv64imafdcmedany.yml deleted file mode 100644 index e4ecd4736a..0000000000 --- a/spec/build/bsps/riscv/riscv/bsprv64imafdcmedany.yml +++ /dev/null @@ -1,19 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: riscv -bsp: rv64imafdc_medany -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -cppflags: [] -enabled-by: true -family: riscv -includes: [] -install: [] -links: -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: grp -source: [] -type: build diff --git a/spec/build/bsps/riscv/riscv/grp.yml b/spec/build/bsps/riscv/riscv/grp.yml index 396f8986ec..43f3a91bee 100644 --- a/spec/build/bsps/riscv/riscv/grp.yml +++ b/spec/build/bsps/riscv/riscv/grp.yml @@ -1,7 +1,10 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause build-type: group +cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG +cppflags: [] +cxxflags: [] enabled-by: true includes: [] install: [] @@ -18,6 +21,8 @@ links: - role: build-dependency uid: ../../optgcc - role: build-dependency + uid: ../optextirqmax +- role: build-dependency uid: ../grp - role: build-dependency uid: ../optrambegin @@ -30,20 +35,30 @@ links: - role: build-dependency uid: objsmp - role: build-dependency - uid: optextirqmax + uid: ../../objmem +- role: build-dependency + uid: ../../optfdtcpyro +- role: build-dependency + uid: ../../optfdtmxsz - role: build-dependency - uid: optfdtcpyro + uid: ../../optfdtro - role: build-dependency - uid: optfdtmxsz + uid: ../../optfdtuboot - role: build-dependency - uid: optfdtro + uid: ../../optdtb - role: build-dependency - uid: optfdtuboot + uid: ../../optdtbheaderpath - role: build-dependency uid: optfrdme310arty - role: build-dependency + uid: optkendrytek210 +- role: build-dependency uid: opthtif - role: build-dependency + uid: optmpfs +- role: build-dependency + uid: optsifiveuart +- role: build-dependency uid: optns16550max - role: build-dependency uid: ../linkcmds diff --git a/spec/build/bsps/riscv/riscv/obj.yml b/spec/build/bsps/riscv/riscv/obj.yml index 2f1ac8051c..b9ad7e95a9 100644 --- a/spec/build/bsps/riscv/riscv/obj.yml +++ b/spec/build/bsps/riscv/riscv/obj.yml @@ -2,7 +2,7 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause build-type: objects cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] cxxflags: [] enabled-by: true @@ -11,12 +11,12 @@ install: - destination: ${BSP_INCLUDEDIR} source: - bsps/riscv/riscv/include/bsp.h - - bsps/riscv/riscv/include/tm27.h - destination: ${BSP_INCLUDEDIR}/bsp source: - bsps/riscv/riscv/include/bsp/fe310-uart.h - bsps/riscv/riscv/include/bsp/irq.h - bsps/riscv/riscv/include/bsp/riscv.h + - bsps/riscv/riscv/include/bsp/k210.h - destination: ${BSP_INCLUDEDIR}/dev/serial source: - bsps/riscv/riscv/include/dev/serial/htif.h @@ -29,6 +29,7 @@ source: - bsps/riscv/riscv/irq/irq.c - bsps/riscv/riscv/start/bsp_fatal_halt.c - bsps/riscv/riscv/start/bspstart.c +- bsps/riscv/shared/start/bspgetworkarea.c - bsps/shared/cache/nocache.c - bsps/shared/dev/btimer/btimer-cpucounter.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c @@ -36,7 +37,6 @@ source: - bsps/shared/irq/irq-default-handler.c - bsps/shared/start/bsp-fdt.c - bsps/shared/start/bspfatal-default.c -- bsps/shared/start/bspgetworkarea-default.c - bsps/shared/start/bspreset-empty.c - bsps/shared/start/gettargethash-default.c type: build diff --git a/spec/build/bsps/riscv/riscv/objsmp.yml b/spec/build/bsps/riscv/riscv/objsmp.yml index 46369f977e..5022525b72 100644 --- a/spec/build/bsps/riscv/riscv/objsmp.yml +++ b/spec/build/bsps/riscv/riscv/objsmp.yml @@ -2,7 +2,7 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause build-type: objects cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] cxxflags: [] enabled-by: diff --git a/spec/build/bsps/riscv/riscv/optextirqmax.yml b/spec/build/bsps/riscv/riscv/optextirqmax.yml deleted file mode 100644 index 9ca6c469ef..0000000000 --- a/spec/build/bsps/riscv/riscv/optextirqmax.yml +++ /dev/null @@ -1,17 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-integer: null -- define: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 64 -default-by-family: [] -default-by-variant: [] -description: | - maximum number of external interrupts supported by the BSP (default 64) -enabled-by: true -format: '{}' -links: [] -name: RISCV_MAXIMUM_EXTERNAL_INTERRUPTS -type: build diff --git a/spec/build/bsps/riscv/riscv/optfdtcpyro.yml b/spec/build/bsps/riscv/riscv/optfdtcpyro.yml deleted file mode 100644 index 5ec59adf4d..0000000000 --- a/spec/build/bsps/riscv/riscv/optfdtcpyro.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-family: [] -default-by-variant: [] -description: | - copy the FDT blob into the read-only load area via bsp_fdt_copy() -enabled-by: true -links: [] -name: BSP_FDT_BLOB_COPY_TO_READ_ONLY_LOAD_AREA -type: build diff --git a/spec/build/bsps/riscv/riscv/optfdtmxsz.yml b/spec/build/bsps/riscv/riscv/optfdtmxsz.yml deleted file mode 100644 index 8a07a2ad08..0000000000 --- a/spec/build/bsps/riscv/riscv/optfdtmxsz.yml +++ /dev/null @@ -1,17 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-integer: null -- define: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 65536 -default-by-family: [] -default-by-variant: [] -description: | - maximum size of the FDT blob in bytes -enabled-by: true -format: '{}' -links: [] -name: BSP_FDT_BLOB_SIZE_MAX -type: build diff --git a/spec/build/bsps/riscv/riscv/optfdtro.yml b/spec/build/bsps/riscv/riscv/optfdtro.yml deleted file mode 100644 index a72bc23c0e..0000000000 --- a/spec/build/bsps/riscv/riscv/optfdtro.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-family: [] -default-by-variant: [] -description: | - place the FDT blob into the read-only data area -enabled-by: true -links: [] -name: BSP_FDT_BLOB_READ_ONLY -type: build diff --git a/spec/build/bsps/riscv/riscv/optfdtuboot.yml b/spec/build/bsps/riscv/riscv/optfdtuboot.yml deleted file mode 100644 index cfe94e577c..0000000000 --- a/spec/build/bsps/riscv/riscv/optfdtuboot.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-family: [] -default-by-variant: [] -description: | - copy the U-Boot provided FDT to an internal storage -enabled-by: true -links: [] -name: BSP_START_COPY_FDT_FROM_U_BOOT -type: build diff --git a/spec/build/bsps/riscv/riscv/optfrdme310arty.yml b/spec/build/bsps/riscv/riscv/optfrdme310arty.yml index ad7215943d..7447fdf8d7 100644 --- a/spec/build/bsps/riscv/riscv/optfrdme310arty.yml +++ b/spec/build/bsps/riscv/riscv/optfrdme310arty.yml @@ -4,13 +4,12 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: false -default-by-family: [] -default-by-variant: -- value: true - variants: - - riscv/frdme310arty.* +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: riscv/frdme310arty + value: true +- enabled-by: true + value: false description: | enables support sifive Freedom E310 Arty board if defined to a non-zero value,otherwise it is disabled (disabled by default) enabled-by: true diff --git a/spec/build/bsps/riscv/riscv/opthtif.yml b/spec/build/bsps/riscv/riscv/opthtif.yml index 13c9876ebd..bf28568fb8 100644 --- a/spec/build/bsps/riscv/riscv/opthtif.yml +++ b/spec/build/bsps/riscv/riscv/opthtif.yml @@ -4,12 +4,12 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: false -default-by-family: [] -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: true description: | - enables the HTIF support if defined to a non-zero value, otherwise it is disabled (disabled by default) + Enable the Host/Target Interface (HTIF) support. enabled-by: true links: [] name: RISCV_ENABLE_HTIF_SUPPORT diff --git a/spec/build/bsps/riscv/riscv/optkendrytek210.yml b/spec/build/bsps/riscv/riscv/optkendrytek210.yml new file mode 100644 index 0000000000..09848cf6e7 --- /dev/null +++ b/spec/build/bsps/riscv/riscv/optkendrytek210.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2022 Alan Cudmore +default: +- enabled-by: riscv/kendrytek210 + value: true +- enabled-by: true + value: false +description: | + enables support for the Kendryte K210 System on Chip if defined to a non-zero value, otherwise it is disabled (disabled by default) +enabled-by: true +links: [] +name: RISCV_ENABLE_KENDRYTE_K210_SUPPORT +type: build diff --git a/spec/build/bsps/riscv/riscv/optmpfs.yml b/spec/build/bsps/riscv/riscv/optmpfs.yml new file mode 100644 index 0000000000..b22d644e82 --- /dev/null +++ b/spec/build/bsps/riscv/riscv/optmpfs.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: riscv/mpfs64imafdc + value: true +- enabled-by: true + value: false +description: | + enables support Microchip PolarFire SoC if defined to a non-zero value,otherwise it is disabled (disabled by default) +enabled-by: true +links: [] +name: RISCV_ENABLE_MPFS_SUPPORT +type: build diff --git a/spec/build/bsps/riscv/riscv/optns16550max.yml b/spec/build/bsps/riscv/riscv/optns16550max.yml index 7331b82545..a610fedefb 100644 --- a/spec/build/bsps/riscv/riscv/optns16550max.yml +++ b/spec/build/bsps/riscv/riscv/optns16550max.yml @@ -4,13 +4,16 @@ actions: - define: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 2 -default-by-family: [] -default-by-variant: -- value: null - variants: - - riscv/frdme310arty.* +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: + - riscv/frdme310arty + - riscv/kendrytek210 + value: null +- enabled-by: riscv/mpfs64imafdc + value: 1 +- enabled-by: true + value: 2 description: | maximum number of NS16550 devices supported by the console driver (2 by default) enabled-by: true diff --git a/spec/build/bsps/riscv/riscv/optsifiveuart.yml b/spec/build/bsps/riscv/riscv/optsifiveuart.yml new file mode 100644 index 0000000000..8ff27d0275 --- /dev/null +++ b/spec/build/bsps/riscv/riscv/optsifiveuart.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: + - riscv/kendrytek210 + - riscv/frdme310arty + value: true +- enabled-by: true + value: false +description: | + enables support Sifive UART if defined to a non-zero value, otherwise it is disabled (disabled by default) +enabled-by: true +links: [] +name: RISCV_ENABLE_SIFIVE_UART_SUPPORT +type: build |