diff options
Diffstat (limited to '')
17 files changed, 17 insertions, 0 deletions
diff --git a/spec/build/bsps/arm/altera-cyclone-v/abi.yml b/spec/build/bsps/arm/altera-cyclone-v/abi.yml index a3a710c97d..7a52d2c74d 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/abi.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/abi.yml @@ -12,6 +12,7 @@ default: - -mfpu=neon - -mfloat-abi=hard - -mtune=cortex-a9 +default-by-family: [] default-by-variant: [] description: | ABI flags diff --git a/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml b/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml index e67ddc129b..9e091ec2c4 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: false +default-by-family: [] default-by-variant: [] description: | define to set ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz, otherwise alt_clk_freq_get() is used diff --git a/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml b/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml index 77dac09116..a37ac80f89 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true +default-by-family: [] default-by-variant: [] description: | enable data cache diff --git a/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml b/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml index a59db43f31..fe2e044f5d 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true +default-by-family: [] default-by-variant: [] description: | enable instruction cache diff --git a/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml b/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml index b800b20428..661d94afe3 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: false +default-by-family: [] default-by-variant: - value: true variants: diff --git a/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml b/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml index 635697cc8a..00d7a4ea92 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true +default-by-family: [] default-by-variant: [] description: | configuration for console (UART 0) diff --git a/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml b/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml index f5c588a330..15a4ff3142 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true +default-by-family: [] default-by-variant: [] description: | configuration for UART 1 diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdtcpyro.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdtcpyro.yml index c26b1ae051..5ec59adf4d 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optfdtcpyro.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optfdtcpyro.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true +default-by-family: [] default-by-variant: [] description: | copy the FDT blob into the read-only load area via bsp_fdt_copy() diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml index f2fc473967..28663616df 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true +default-by-family: [] default-by-variant: [] description: | define if FDT is supported diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdtmxsz.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdtmxsz.yml index 14af766230..f3b2504e02 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optfdtmxsz.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optfdtmxsz.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: 262144 +default-by-family: [] default-by-variant: [] description: | maximum size of the FDT blob in bytes diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdtro.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdtro.yml index a61bb2924b..a72bc23c0e 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optfdtro.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optfdtro.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true +default-by-family: [] default-by-variant: [] description: | place the FDT blob into the read-only data area diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdtuboot.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdtuboot.yml index 5805e912ff..cfe94e577c 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optfdtuboot.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optfdtuboot.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true +default-by-family: [] default-by-variant: [] description: | copy the U-Boot provided FDT to an internal storage diff --git a/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml b/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml index ee8097aa3b..8053c93c47 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: 100000 +default-by-family: [] default-by-variant: [] description: | speed for I2C0 in HZ diff --git a/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml b/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml index 2d36d5f930..a4540d0e4b 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true +default-by-family: [] default-by-variant: [] description: | Number of configured I2C buses. Note that each bus has to be configured in an apropriate i2cdrv_config array. diff --git a/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml b/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml index efd1ea2b2a..52f469c2d9 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: false +default-by-family: [] default-by-variant: [] description: | reset vector address for BSP start diff --git a/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml b/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml index b5f577ffc3..abd3502e5c 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: 115200 +default-by-family: [] default-by-variant: [] description: | baud for UARTs diff --git a/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml b/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml index 152668b2d9..3f264d3cbb 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml @@ -6,6 +6,7 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: true +default-by-family: [] default-by-variant: [] description: | enable usage of interrupts for the UART modules |