summaryrefslogtreecommitdiffstats
path: root/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml
blob: b800b204281e0521b93665c3fb2f0777185e8b40 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-boolean: null
- define-condition: null
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-variant:
- value: true
  variants:
  - arm/.*qemu
description: |
  This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing.  This can significantly reduce simulation times.
enabled-by: true
links: []
name: CLOCK_DRIVER_USE_FAST_IDLE
type: build