diff options
Diffstat (limited to 'spec/build/bsps/arm/altera-cyclone-v')
15 files changed, 63 insertions, 49 deletions
diff --git a/spec/build/bsps/arm/altera-cyclone-v/abi.yml b/spec/build/bsps/arm/altera-cyclone-v/abi.yml index a3a710c97d..280b42de1e 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/abi.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/abi.yml @@ -5,14 +5,15 @@ actions: - env-append: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG default: -- -march=armv7-a -- -mthumb -- -mfpu=neon -- -mfloat-abi=hard -- -mtune=cortex-a9 -default-by-variant: [] +- enabled-by: true + value: + - -march=armv7-a + - -mthumb + - -mfpu=neon + - -mfloat-abi=hard + - -mtune=cortex-a9 description: | ABI flags enabled-by: true diff --git a/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml b/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml index f1f39ff6b2..74a917c533 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml @@ -4,7 +4,7 @@ bsp: altcycv_devkit build-type: bsp cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] enabled-by: true family: altera-cyclone-v @@ -13,7 +13,6 @@ install: - destination: ${BSP_INCLUDEDIR} source: - bsps/arm/altera-cyclone-v/include/bsp.h - - bsps/arm/altera-cyclone-v/include/tm27.h - destination: ${BSP_INCLUDEDIR}/bsp source: - bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h diff --git a/spec/build/bsps/arm/altera-cyclone-v/objsmp.yml b/spec/build/bsps/arm/altera-cyclone-v/objsmp.yml index bf0c99d21f..acbef94765 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/objsmp.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/objsmp.yml @@ -2,7 +2,7 @@ SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause build-type: objects cflags: [] copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +- Copyright (C) 2020 embedded brains GmbH & Co. KG cppflags: [] cxxflags: [] enabled-by: diff --git a/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml b/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml index e67ddc129b..205be52863 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml @@ -4,9 +4,10 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: false -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: false description: | define to set ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz, otherwise alt_clk_freq_get() is used enabled-by: true diff --git a/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml b/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml index 77dac09116..f47823b41f 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml @@ -4,9 +4,10 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: true description: | enable data cache enabled-by: true diff --git a/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml b/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml index a59db43f31..d997b69897 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml @@ -4,9 +4,10 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: true description: | enable instruction cache enabled-by: true diff --git a/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml b/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml index b800b20428..f0b83e1402 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml @@ -4,12 +4,15 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: false -default-by-variant: -- value: true - variants: - - arm/.*qemu +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: + - arm/lm3s6965_qemu + - arm/realview_pbx_a9_qemu + - arm/xilinx_zynq_a9_qemu + value: true +- enabled-by: true + value: false description: | This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing. This can significantly reduce simulation times. enabled-by: true diff --git a/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml b/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml index 635697cc8a..1033640bcc 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml @@ -4,9 +4,10 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: true description: | configuration for console (UART 0) enabled-by: true diff --git a/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml b/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml index f5c588a330..acf97aa2de 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml @@ -4,9 +4,10 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: true description: | configuration for UART 1 enabled-by: true diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml index f2fc473967..734b52f668 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml @@ -4,9 +4,10 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: true description: | define if FDT is supported enabled-by: true diff --git a/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml b/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml index ee8097aa3b..49af6b2aac 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml @@ -4,9 +4,10 @@ actions: - define: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 100000 -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 100000 description: | speed for I2C0 in HZ enabled-by: true diff --git a/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml b/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml index 2d36d5f930..2e17fb9deb 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml @@ -4,9 +4,10 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: true description: | Number of configured I2C buses. Note that each bus has to be configured in an apropriate i2cdrv_config array. enabled-by: true diff --git a/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml b/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml index efd1ea2b2a..206a6f2801 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml @@ -4,9 +4,10 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: false -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: false description: | reset vector address for BSP start enabled-by: true diff --git a/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml b/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml index b5f577ffc3..64f17b68f0 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml @@ -4,9 +4,10 @@ actions: - define: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: 115200 -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 115200 description: | baud for UARTs enabled-by: true diff --git a/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml b/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml index 152668b2d9..0dfc3c7a0a 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml @@ -4,9 +4,10 @@ actions: - define-condition: null build-type: option copyrights: -- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: true -default-by-variant: [] +- Copyright (C) 2020 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: true description: | enable usage of interrupts for the UART modules enabled-by: true |