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-rw-r--r--cpukit/score/cpu/riscv/include/rtems/asm.h12
-rw-r--r--cpukit/score/cpu/riscv/riscv-exception-handler.S2
2 files changed, 12 insertions, 2 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/asm.h b/cpukit/score/cpu/riscv/include/rtems/asm.h
index c3be827be0..c4abc76a27 100644
--- a/cpukit/score/cpu/riscv/include/rtems/asm.h
+++ b/cpukit/score/cpu/riscv/include/rtems/asm.h
@@ -131,6 +131,16 @@
#endif /* __riscv_xlen */
+#ifdef __riscv_cmodel_medany
+
+#define LADDR lla
+
+#else /* !__riscv_cmodel_medany */
+
+#define LADDR la
+
+#endif /* __riscv_cmodel_medany */
+
#if __riscv_flen == 32
#define FLREG flw
@@ -167,7 +177,7 @@
#ifdef RTEMS_SMP
csrr \REG, mscratch
#else
- la \REG, _Per_CPU_Information
+ LADDR \REG, _Per_CPU_Information
#endif
.endm
diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S
index 05bad455ac..875566cb23 100644
--- a/cpukit/score/cpu/riscv/riscv-exception-handler.S
+++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S
@@ -128,7 +128,7 @@ SYM(ISR_Handler):
mv a1, sp
/* calculate the offset */
- la t5, bsp_start_vector_table_begin
+ LADDR t5, bsp_start_vector_table_begin
#if __riscv_xlen == 32
slli t6, a0, 2
#else /* xlen = 64 */