diff options
Diffstat (limited to 'cpukit/score/cpu/x86_64/include/rtems')
4 files changed, 43 insertions, 45 deletions
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h index bea8e05e39..b26fb4c8ad 100644 --- a/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h @@ -144,7 +144,7 @@ typedef struct { #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE #define CPU_STACK_MINIMUM_SIZE (1024*4) #define CPU_SIZEOF_POINTER 8 -#define CPU_ALIGNMENT 8 +#define CPU_ALIGNMENT 16 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT #define CPU_STACK_ALIGNMENT 16 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES @@ -177,12 +177,12 @@ typedef struct { (void) _level; /* Prevent -Wunused-but-set-variable */ \ } -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled(uint32_t level) +static inline bool _CPU_ISR_Is_enabled(uint32_t level) { return (level & EFLAGS_INTR_ENABLE) != 0; } -RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level(uint32_t new_level) +static inline void _CPU_ISR_Set_level(uint32_t new_level) { if ( new_level ) { amd64_disable_interrupts(); @@ -192,7 +192,7 @@ RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level(uint32_t new_level) } } -RTEMS_INLINE_ROUTINE uint32_t _CPU_ISR_Get_level(void) +static inline uint32_t _CPU_ISR_Get_level(void) { uint64_t rflags; @@ -304,15 +304,6 @@ uint32_t _CPU_Counter_frequency( void ); CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - #ifdef RTEMS_SMP * uint32_t _CPU_SMP_Initialize( void ); diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h index 4ad50b9f42..10e0887cb9 100644 --- a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h @@ -31,7 +31,7 @@ #include <rtems/score/basedefs.h> -RTEMS_INLINE_ROUTINE uint8_t inport_byte(uint16_t port) +static inline uint8_t inport_byte(uint16_t port) { uint8_t ret; __asm__ volatile ( "inb %1, %0" @@ -40,12 +40,12 @@ RTEMS_INLINE_ROUTINE uint8_t inport_byte(uint16_t port) return ret; } -RTEMS_INLINE_ROUTINE void outport_byte(uint16_t port, uint8_t val) +static inline void outport_byte(uint16_t port, uint8_t val) { __asm__ volatile ( "outb %0, %1" : : "a" (val), "Nd" (port) ); } -RTEMS_INLINE_ROUTINE uint16_t amd64_get_cs(void) +static inline uint16_t amd64_get_cs(void) { uint16_t segment = 0; @@ -54,12 +54,12 @@ RTEMS_INLINE_ROUTINE uint16_t amd64_get_cs(void) return segment; } -RTEMS_INLINE_ROUTINE void amd64_set_cr3(uint64_t segment) +static inline void amd64_set_cr3(uint64_t segment) { __asm__ volatile ( "movq %0, %%cr3" : "=r" (segment) : "0" (segment) ); } -RTEMS_INLINE_ROUTINE void cpuid( +static inline void cpuid( uint32_t code, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx ) { __asm__ volatile ( "cpuid" @@ -67,7 +67,7 @@ RTEMS_INLINE_ROUTINE void cpuid( : "a" (code) ); } -RTEMS_INLINE_ROUTINE uint64_t rdmsr(uint32_t msr) +static inline uint64_t rdmsr(uint32_t msr) { uint32_t low, high; __asm__ volatile ( "rdmsr" : @@ -76,23 +76,23 @@ RTEMS_INLINE_ROUTINE uint64_t rdmsr(uint32_t msr) return low | (uint64_t) high << 32; } -RTEMS_INLINE_ROUTINE void wrmsr(uint32_t msr, uint32_t low, uint32_t high) +static inline void wrmsr(uint32_t msr, uint32_t low, uint32_t high) { __asm__ volatile ( "wrmsr" : : "a" (low), "d" (high), "c" (msr) ); } -RTEMS_INLINE_ROUTINE void amd64_enable_interrupts(void) +static inline void amd64_enable_interrupts(void) { __asm__ volatile ( "sti" ); } -RTEMS_INLINE_ROUTINE void amd64_disable_interrupts(void) +static inline void amd64_disable_interrupts(void) { __asm__ volatile ( "cli" ); } -RTEMS_INLINE_ROUTINE void stub_io_wait(void) +static inline void stub_io_wait(void) { /* XXX: This likely won't be required on any modern boards, but this function * exists so it's easier to find all the places it may be used. diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/x86_64/include/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include <rtems/score/cpustdatomic.h> - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h index d3a4b848e6..d4b7a71009 100644 --- a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h @@ -8,7 +8,7 @@ * Copyright (c) 2018. * Amaan Cheval <amaan.cheval@gmail.com> * - * Copyright (c) 2013, 2016 embedded brains GmbH + * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -32,6 +32,8 @@ #define CPU_PER_CPU_CONTROL_SIZE 0 +#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20 + #ifndef ASM #ifdef __cplusplus @@ -40,28 +42,47 @@ extern "C" { RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); -RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern ) +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) { + (void) pattern; + /* TODO */ } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Context_validate( uintptr_t pattern ) { - __asm__ volatile ( ".word 0" ); -} + (void) pattern; -RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern ) -{ while (1) { /* TODO */ } } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_illegal( void ) +{ + __asm__ volatile ( ".word 0" ); +} + +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } +static inline void _CPU_Use_thread_local_storage( + const Context_Control *context +) +{ + (void) context; +} + +static inline void *_CPU_Get_TLS_thread_pointer( + const Context_Control *context +) +{ + (void) context; + return NULL; +} + #ifdef __cplusplus } #endif |