diff options
Diffstat (limited to 'cpukit/score/cpu/riscv/riscv-exception-handler.S')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-exception-handler.S | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index 844d417738..b15bab49c7 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -62,6 +62,9 @@ SYM(ISR_Handler): csrr a2, mepc GET_SELF_CPU_CONTROL s0 SREG s1, RISCV_INTERRUPT_FRAME_S1(sp) +#if __riscv_flen > 0 + frcsr s1 +#endif SREG ra, RISCV_INTERRUPT_FRAME_RA(sp) SREG a3, RISCV_INTERRUPT_FRAME_A3(sp) SREG a4, RISCV_INTERRUPT_FRAME_A4(sp) @@ -77,6 +80,29 @@ SYM(ISR_Handler): SREG t6, RISCV_INTERRUPT_FRAME_T6(sp) SREG a1, RISCV_INTERRUPT_FRAME_MSTATUS(sp) SREG a2, RISCV_INTERRUPT_FRAME_MEPC(sp) +#if __riscv_flen > 0 + sw s1, RISCV_INTERRUPT_FRAME_FCSR(sp) + FSREG ft0, RISCV_INTERRUPT_FRAME_FT0(sp) + FSREG ft1, RISCV_INTERRUPT_FRAME_FT1(sp) + FSREG ft2, RISCV_INTERRUPT_FRAME_FT2(sp) + FSREG ft3, RISCV_INTERRUPT_FRAME_FT3(sp) + FSREG ft4, RISCV_INTERRUPT_FRAME_FT4(sp) + FSREG ft5, RISCV_INTERRUPT_FRAME_FT5(sp) + FSREG ft6, RISCV_INTERRUPT_FRAME_FT6(sp) + FSREG ft7, RISCV_INTERRUPT_FRAME_FT7(sp) + FSREG ft8, RISCV_INTERRUPT_FRAME_FT8(sp) + FSREG ft9, RISCV_INTERRUPT_FRAME_FT9(sp) + FSREG ft10, RISCV_INTERRUPT_FRAME_FT10(sp) + FSREG ft11, RISCV_INTERRUPT_FRAME_FT11(sp) + FSREG fa0, RISCV_INTERRUPT_FRAME_FA0(sp) + FSREG fa1, RISCV_INTERRUPT_FRAME_FA1(sp) + FSREG fa2, RISCV_INTERRUPT_FRAME_FA2(sp) + FSREG fa3, RISCV_INTERRUPT_FRAME_FA3(sp) + FSREG fa4, RISCV_INTERRUPT_FRAME_FA4(sp) + FSREG fa5, RISCV_INTERRUPT_FRAME_FA5(sp) + FSREG fa6, RISCV_INTERRUPT_FRAME_FA6(sp) + FSREG fa7, RISCV_INTERRUPT_FRAME_FA7(sp) +#endif /* FIXME Only handle interrupts for now (MSB = 1) */ andi a0, a0, 0xf @@ -191,6 +217,30 @@ SYM(ISR_Handler): LREG t6, RISCV_INTERRUPT_FRAME_T6(sp) csrw mstatus, a0 csrw mepc, a1 +#if __riscv_flen > 0 + lw a0, RISCV_INTERRUPT_FRAME_FCSR(sp) + FLREG ft0, RISCV_INTERRUPT_FRAME_FT0(sp) + FLREG ft1, RISCV_INTERRUPT_FRAME_FT1(sp) + FLREG ft2, RISCV_INTERRUPT_FRAME_FT2(sp) + FLREG ft3, RISCV_INTERRUPT_FRAME_FT3(sp) + FLREG ft4, RISCV_INTERRUPT_FRAME_FT4(sp) + FLREG ft5, RISCV_INTERRUPT_FRAME_FT5(sp) + FLREG ft6, RISCV_INTERRUPT_FRAME_FT6(sp) + FLREG ft7, RISCV_INTERRUPT_FRAME_FT7(sp) + FLREG ft8, RISCV_INTERRUPT_FRAME_FT8(sp) + FLREG ft9, RISCV_INTERRUPT_FRAME_FT9(sp) + FLREG ft10, RISCV_INTERRUPT_FRAME_FT10(sp) + FLREG ft11, RISCV_INTERRUPT_FRAME_FT11(sp) + FLREG fa0, RISCV_INTERRUPT_FRAME_FA0(sp) + FLREG fa1, RISCV_INTERRUPT_FRAME_FA1(sp) + FLREG fa2, RISCV_INTERRUPT_FRAME_FA2(sp) + FLREG fa3, RISCV_INTERRUPT_FRAME_FA3(sp) + FLREG fa4, RISCV_INTERRUPT_FRAME_FA4(sp) + FLREG fa5, RISCV_INTERRUPT_FRAME_FA5(sp) + FLREG fa6, RISCV_INTERRUPT_FRAME_FA6(sp) + FLREG fa7, RISCV_INTERRUPT_FRAME_FA7(sp) + fscsr a0 +#endif LREG a0, RISCV_INTERRUPT_FRAME_A0(sp) LREG a1, RISCV_INTERRUPT_FRAME_A1(sp) |