diff options
Diffstat (limited to 'cpukit/score/cpu/riscv/riscv-context-validate.S')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-validate.S | 178 |
1 files changed, 177 insertions, 1 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-context-validate.S b/cpukit/score/cpu/riscv/riscv-context-validate.S index 1c9d3d856c..bd2a7f0317 100644 --- a/cpukit/score/cpu/riscv/riscv-context-validate.S +++ b/cpukit/score/cpu/riscv/riscv-context-validate.S @@ -61,9 +61,18 @@ #define T4_OFFSET OFFSET(25) #define T5_OFFSET OFFSET(26) #define T6_OFFSET OFFSET(27) +#define TMP_OFFSET OFFSET(28) + +#if __riscv_flen == 32 +#define FOFFSET(i) (OFFSET(29) + (i) * 4) +#elif __riscv_flen == 64 +#define FOFFSET(i) (OFFSET(29) + (i) * 8) +#else +#define FOFFSET(i) OFFSET(29) +#endif /* __riscv_flen */ #define FRAME_SIZE \ - ((OFFSET(28) + CPU_STACK_ALIGNMENT - 1) & ~(CPU_STACK_ALIGNMENT - 1)) + ((FOFFSET(32) + CPU_STACK_ALIGNMENT - 1) & ~(CPU_STACK_ALIGNMENT - 1)) .section .text, "ax", @progbits .align 2 @@ -73,6 +82,7 @@ SYM(_CPU_Context_validate): addi sp, sp, -FRAME_SIZE /* Save */ + SREG ra, RA_OFFSET(sp) SREG t0, T0_OFFSET(sp) SREG t1, T1_OFFSET(sp) @@ -102,7 +112,43 @@ SYM(_CPU_Context_validate): SREG t5, T5_OFFSET(sp) SREG t6, T6_OFFSET(sp) +#if __riscv_flen > 0 + FSREG f0, FOFFSET(0)(sp) + FSREG f1, FOFFSET(1)(sp) + FSREG f2, FOFFSET(2)(sp) + FSREG f3, FOFFSET(3)(sp) + FSREG f4, FOFFSET(4)(sp) + FSREG f5, FOFFSET(5)(sp) + FSREG f6, FOFFSET(6)(sp) + FSREG f7, FOFFSET(7)(sp) + FSREG f8, FOFFSET(8)(sp) + FSREG f9, FOFFSET(9)(sp) + FSREG f10, FOFFSET(10)(sp) + FSREG f11, FOFFSET(11)(sp) + FSREG f12, FOFFSET(12)(sp) + FSREG f13, FOFFSET(13)(sp) + FSREG f14, FOFFSET(14)(sp) + FSREG f15, FOFFSET(15)(sp) + FSREG f16, FOFFSET(16)(sp) + FSREG f17, FOFFSET(17)(sp) + FSREG f18, FOFFSET(18)(sp) + FSREG f19, FOFFSET(19)(sp) + FSREG f20, FOFFSET(20)(sp) + FSREG f21, FOFFSET(21)(sp) + FSREG f22, FOFFSET(22)(sp) + FSREG f23, FOFFSET(23)(sp) + FSREG f24, FOFFSET(24)(sp) + FSREG f25, FOFFSET(25)(sp) + FSREG f26, FOFFSET(26)(sp) + FSREG f27, FOFFSET(27)(sp) + FSREG f28, FOFFSET(28)(sp) + FSREG f29, FOFFSET(29)(sp) + FSREG f30, FOFFSET(30)(sp) + FSREG f31, FOFFSET(31)(sp) +#endif /* __riscv_flen */ + /* Fill */ + addi ra, a0, 1 /* sp must remain as is */ /* gp must remain as is */ @@ -136,7 +182,51 @@ SYM(_CPU_Context_validate): xor t5, gp, a0 xor t6, tp, a0 +#if __riscv_flen > 0 + andi t0, a0, 0x1f + fsflags t0 + + .macro fill_f reg, inc + addi t0, a0, 24 + \inc + FMVYX \reg, t0 + .endm + + fill_f f0, 0 + fill_f f1, 1 + fill_f f2, 2 + fill_f f3, 3 + fill_f f4, 4 + fill_f f5, 5 + fill_f f6, 6 + fill_f f7, 7 + fill_f f8, 8 + fill_f f9, 9 + fill_f f10, 10 + fill_f f11, 11 + fill_f f12, 12 + fill_f f13, 13 + fill_f f14, 14 + fill_f f15, 15 + fill_f f16, 16 + fill_f f17, 17 + fill_f f18, 18 + fill_f f19, 19 + fill_f f20, 20 + fill_f f21, 21 + fill_f f22, 22 + fill_f f23, 23 + fill_f f24, 24 + fill_f f25, 25 + fill_f f26, 26 + fill_f f27, 27 + fill_f f28, 28 + fill_f f29, 29 + fill_f f30, 30 + fill_f f31, 31 +#endif /* __riscv_flen */ + /* Check */ + .Lcheck: .macro check_register reg, inc addi t0, a0, \inc @@ -176,10 +266,61 @@ SYM(_CPU_Context_validate): xor t0, tp, a0 bne t6, t0, .Lrestore +#if __riscv_flen > 0 + SREG t1, TMP_OFFSET(sp) + frflags t0 + andi t1, a0, 0x1f + xor t0, t1, t0 + LREG t1, TMP_OFFSET(sp) + bnez t0, .Lrestore + + + .macro check_f reg, inc + FMVXY t0, \reg + addi t0, t0, -24 - \inc + bne t0, a0, .Lrestore + .endm + + check_f f0, 0 + check_f f1, 1 + check_f f2, 2 + check_f f3, 3 + check_f f4, 4 + check_f f5, 5 + check_f f6, 6 + check_f f7, 7 + check_f f8, 8 + check_f f9, 9 + check_f f10, 10 + check_f f11, 11 + check_f f12, 12 + check_f f13, 13 + check_f f14, 14 + check_f f15, 15 + check_f f16, 16 + check_f f17, 17 + check_f f18, 18 + check_f f19, 19 + check_f f20, 20 + check_f f21, 21 + check_f f22, 22 + check_f f23, 23 + check_f f24, 24 + check_f f25, 25 + check_f f26, 26 + check_f f27, 27 + check_f f28, 28 + check_f f29, 29 + check_f f30, 30 + check_f f31, 31 +#endif /* __riscv_flen */ + j .Lcheck /* Restore */ + .Lrestore: + LREG ra, RA_OFFSET(sp) LREG t0, T0_OFFSET(sp) LREG t1, T1_OFFSET(sp) @@ -209,5 +350,40 @@ SYM(_CPU_Context_validate): LREG t5, T5_OFFSET(sp) LREG t6, T6_OFFSET(sp) +#if __riscv_flen > 0 + FLREG f0, FOFFSET(0)(sp) + FLREG f1, FOFFSET(1)(sp) + FLREG f2, FOFFSET(2)(sp) + FLREG f3, FOFFSET(3)(sp) + FLREG f4, FOFFSET(4)(sp) + FLREG f5, FOFFSET(5)(sp) + FLREG f6, FOFFSET(6)(sp) + FLREG f7, FOFFSET(7)(sp) + FLREG f8, FOFFSET(8)(sp) + FLREG f9, FOFFSET(9)(sp) + FLREG f10, FOFFSET(10)(sp) + FLREG f11, FOFFSET(11)(sp) + FLREG f12, FOFFSET(12)(sp) + FLREG f13, FOFFSET(13)(sp) + FLREG f14, FOFFSET(14)(sp) + FLREG f15, FOFFSET(15)(sp) + FLREG f16, FOFFSET(16)(sp) + FLREG f17, FOFFSET(17)(sp) + FLREG f18, FOFFSET(18)(sp) + FLREG f19, FOFFSET(19)(sp) + FLREG f20, FOFFSET(20)(sp) + FLREG f21, FOFFSET(21)(sp) + FLREG f22, FOFFSET(22)(sp) + FLREG f23, FOFFSET(23)(sp) + FLREG f24, FOFFSET(24)(sp) + FLREG f25, FOFFSET(25)(sp) + FLREG f26, FOFFSET(26)(sp) + FLREG f27, FOFFSET(27)(sp) + FLREG f28, FOFFSET(28)(sp) + FLREG f29, FOFFSET(29)(sp) + FLREG f30, FOFFSET(30)(sp) + FLREG f31, FOFFSET(31)(sp) +#endif /* __riscv_flen */ + addi sp, sp, FRAME_SIZE ret |