diff options
Diffstat (limited to 'cpukit/score/cpu/riscv/riscv-context-switch.S')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-switch.S | 46 |
1 files changed, 37 insertions, 9 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S index 3626155409..2be34342d9 100644 --- a/cpukit/score/cpu/riscv/riscv-context-switch.S +++ b/cpukit/score/cpu/riscv/riscv-context-switch.S @@ -38,13 +38,15 @@ PUBLIC(_CPU_Context_switch) PUBLIC(_CPU_Context_restore) -PUBLIC(_CPU_Context_restore_fp) -PUBLIC(_CPU_Context_save_fp) SYM(_CPU_Context_switch): GET_SELF_CPU_CONTROL a2 lw a3, PER_CPU_ISR_DISPATCH_DISABLE(a2) +#if __riscv_flen > 0 + frcsr a4 +#endif + SREG ra, RISCV_CONTEXT_RA(a0) SREG sp, RISCV_CONTEXT_SP(a0) SREG s0, RISCV_CONTEXT_S0(a0) @@ -60,6 +62,22 @@ SYM(_CPU_Context_switch): SREG s10, RISCV_CONTEXT_S10(a0) SREG s11, RISCV_CONTEXT_S11(a0) +#if __riscv_flen > 0 + sw a4, RISCV_CONTEXT_FCSR(a0) + FSREG fs0, RISCV_CONTEXT_FS0(a0) + FSREG fs1, RISCV_CONTEXT_FS1(a0) + FSREG fs2, RISCV_CONTEXT_FS2(a0) + FSREG fs3, RISCV_CONTEXT_FS3(a0) + FSREG fs4, RISCV_CONTEXT_FS4(a0) + FSREG fs5, RISCV_CONTEXT_FS5(a0) + FSREG fs6, RISCV_CONTEXT_FS6(a0) + FSREG fs7, RISCV_CONTEXT_FS7(a0) + FSREG fs8, RISCV_CONTEXT_FS8(a0) + FSREG fs9, RISCV_CONTEXT_FS9(a0) + FSREG fs10, RISCV_CONTEXT_FS10(a0) + FSREG fs11, RISCV_CONTEXT_FS11(a0) +#endif + sw a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a0) .Lrestore: @@ -81,6 +99,23 @@ SYM(_CPU_Context_switch): LREG s10, RISCV_CONTEXT_S10(a1) LREG s11, RISCV_CONTEXT_S11(a1) +#if __riscv_flen > 0 + lw a4, RISCV_CONTEXT_FCSR(a1) + FLREG fs0, RISCV_CONTEXT_FS0(a1) + FLREG fs1, RISCV_CONTEXT_FS1(a1) + FLREG fs2, RISCV_CONTEXT_FS2(a1) + FLREG fs3, RISCV_CONTEXT_FS3(a1) + FLREG fs4, RISCV_CONTEXT_FS4(a1) + FLREG fs5, RISCV_CONTEXT_FS5(a1) + FLREG fs6, RISCV_CONTEXT_FS6(a1) + FLREG fs7, RISCV_CONTEXT_FS7(a1) + FLREG fs8, RISCV_CONTEXT_FS8(a1) + FLREG fs9, RISCV_CONTEXT_FS9(a1) + FLREG fs10, RISCV_CONTEXT_FS10(a1) + FLREG fs11, RISCV_CONTEXT_FS11(a1) + fscsr a4 +#endif + sw a3, PER_CPU_ISR_DISPATCH_DISABLE(a2) ret @@ -89,10 +124,3 @@ SYM(_CPU_Context_restore): mv a1, a0 GET_SELF_CPU_CONTROL a2 j .Lrestore - - /* TODO no FP support for riscv32 yet */ - SYM(_CPU_Context_restore_fp): - nop - - SYM(_CPU_Context_save_fp): - nop |