diff options
Diffstat (limited to 'cpukit/score/cpu/riscv/include')
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/asm.h | 32 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 61 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 131 |
3 files changed, 184 insertions, 40 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/asm.h b/cpukit/score/cpu/riscv/include/rtems/asm.h index 024091375d..259fe3de2c 100644 --- a/cpukit/score/cpu/riscv/include/rtems/asm.h +++ b/cpukit/score/cpu/riscv/include/rtems/asm.h @@ -131,6 +131,38 @@ #endif /* __riscv_xlen */ +#if __riscv_flen == 32 + +#define FLREG flw + +#define FSREG fsw + +#define FMVYX fmv.s.x + +#define FMVXY fmv.x.s + +#elif __riscv_flen == 64 + +#define FLREG fld + +#define FSREG fsd + +#if __riscv_xlen == 32 + +#define FMVYX fmv.s.x + +#define FMVXY fmv.x.s + +#elif __riscv_xlen == 64 + +#define FMVYX fmv.d.x + +#define FMVXY fmv.x.d + +#endif /* __riscv_xlen */ + +#endif /* __riscv_flen */ + .macro GET_SELF_CPU_CONTROL REG #ifdef RTEMS_SMP csrr \REG, mscratch diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 124bbae1d4..2220161c9e 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -64,8 +64,6 @@ extern "C" { #define CPU_LITTLE_ENDIAN TRUE #define CPU_MODES_INTERRUPT_MASK 0x0000000000000001 -#define CPU_CONTEXT_FP_SIZE 0 - #define CPU_PER_CPU_CONTROL_SIZE 0 #define CPU_CACHE_LINE_BYTES 64 @@ -100,6 +98,12 @@ extern "C" { #ifndef ASM +#if __riscv_flen == 32 +typedef float RISCV_Float; +#elif __riscv_flen == 64 +typedef double RISCV_Float; +#endif + typedef struct { #ifdef RTEMS_SMP volatile uint32_t is_executing; @@ -122,18 +126,26 @@ typedef struct { uintptr_t s9; uintptr_t s10; uintptr_t s11; +#if __riscv_flen > 0 + uint32_t fcsr; + RISCV_Float fs0; + RISCV_Float fs1; + RISCV_Float fs2; + RISCV_Float fs3; + RISCV_Float fs4; + RISCV_Float fs5; + RISCV_Float fs6; + RISCV_Float fs7; + RISCV_Float fs8; + RISCV_Float fs9; + RISCV_Float fs10; + RISCV_Float fs11; +#endif } Context_Control; #define _CPU_Context_Get_SP( _context ) \ (_context)->sp -typedef struct { - /** TODO FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -Context_Control_fp _CPU_Null_fp_context; - #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE @@ -204,15 +216,6 @@ void _CPU_Context_Initialize( #define _CPU_Context_Restart_self( _the_context ) \ _CPU_Context_restore( (_the_context) ) - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) RTEMS_NO_RETURN; #define CPU_USE_GENERIC_BITFIELD_CODE TRUE @@ -326,28 +329,6 @@ void _CPU_Context_restore( Context_Control *new_context ) RTEMS_NO_RETURN; -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - /* The following routine swaps the endian format of an unsigned int. * It must be static because it is referenced indirectly. * diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index c56e1acab2..2bff71567c 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -78,11 +78,46 @@ #define RISCV_INTERRUPT_FRAME_T4 60 #define RISCV_INTERRUPT_FRAME_T5 64 #define RISCV_INTERRUPT_FRAME_T6 68 + +#if __riscv_flen == 0 + #define RISCV_INTERRUPT_FRAME_A0 72 #define RISCV_INTERRUPT_FRAME_A1 76 #define CPU_INTERRUPT_FRAME_SIZE 80 +#elif __riscv_flen == 32 + +#define RISCV_CONTEXT_FCSR 68 + +#define RISCV_CONTEXT_F( x ) (72 + 4 * (x)) + +#define RISCV_INTERRUPT_FRAME_FCSR 72 + +#define RISCV_INTERRUPT_FRAME_F( x ) (76 + 4 * (x)) + +#define RISCV_INTERRUPT_FRAME_A0 156 +#define RISCV_INTERRUPT_FRAME_A1 160 + +#define CPU_INTERRUPT_FRAME_SIZE 176 + +#elif __riscv_flen == 64 + +#define RISCV_CONTEXT_FCSR 68 + +#define RISCV_CONTEXT_F( x ) (72 + 8 * (x)) + +#define RISCV_INTERRUPT_FRAME_FCSR 72 + +#define RISCV_INTERRUPT_FRAME_F( x ) (80 + 8 * (x)) + +#define RISCV_INTERRUPT_FRAME_A0 240 +#define RISCV_INTERRUPT_FRAME_A1 244 + +#define CPU_INTERRUPT_FRAME_SIZE 256 + +#endif /* __riscv_flen */ + #elif __riscv_xlen == 64 #define RISCV_CONTEXT_RA 8 @@ -119,13 +154,86 @@ #define RISCV_INTERRUPT_FRAME_T4 120 #define RISCV_INTERRUPT_FRAME_T5 128 #define RISCV_INTERRUPT_FRAME_T6 136 + +#if __riscv_flen == 0 + #define RISCV_INTERRUPT_FRAME_A0 144 #define RISCV_INTERRUPT_FRAME_A1 152 #define CPU_INTERRUPT_FRAME_SIZE 160 +#elif __riscv_flen == 32 + +#define RISCV_CONTEXT_FCSR 128 + +#define RISCV_CONTEXT_F( x ) (132 + 4 * (x)) + +#define RISCV_INTERRUPT_FRAME_FCSR 144 + +#define RISCV_INTERRUPT_FRAME_F( x ) (148 + 4 * (x)) + +#define RISCV_INTERRUPT_FRAME_A0 232 +#define RISCV_INTERRUPT_FRAME_A1 240 + +#define CPU_INTERRUPT_FRAME_SIZE 256 + +#elif __riscv_flen == 64 + +#define RISCV_CONTEXT_FCSR 128 + +#define RISCV_CONTEXT_F( x ) (136 + 8 * (x)) + +#define RISCV_INTERRUPT_FRAME_FCSR 144 + +#define RISCV_INTERRUPT_FRAME_F( x ) (152 + 8 * (x)) + +#define RISCV_INTERRUPT_FRAME_A0 312 +#define RISCV_INTERRUPT_FRAME_A1 320 + +#define CPU_INTERRUPT_FRAME_SIZE 336 + +#endif /* __riscv_flen */ + #endif /* __riscv_xlen */ +#if __riscv_flen > 0 + +#define RISCV_CONTEXT_FS0 RISCV_CONTEXT_F( 0 ) +#define RISCV_CONTEXT_FS1 RISCV_CONTEXT_F( 1 ) +#define RISCV_CONTEXT_FS2 RISCV_CONTEXT_F( 2 ) +#define RISCV_CONTEXT_FS3 RISCV_CONTEXT_F( 3 ) +#define RISCV_CONTEXT_FS4 RISCV_CONTEXT_F( 4 ) +#define RISCV_CONTEXT_FS5 RISCV_CONTEXT_F( 5 ) +#define RISCV_CONTEXT_FS6 RISCV_CONTEXT_F( 6 ) +#define RISCV_CONTEXT_FS7 RISCV_CONTEXT_F( 7 ) +#define RISCV_CONTEXT_FS8 RISCV_CONTEXT_F( 8 ) +#define RISCV_CONTEXT_FS9 RISCV_CONTEXT_F( 9 ) +#define RISCV_CONTEXT_FS10 RISCV_CONTEXT_F( 10 ) +#define RISCV_CONTEXT_FS11 RISCV_CONTEXT_F( 11 ) + +#define RISCV_INTERRUPT_FRAME_FT0 RISCV_INTERRUPT_FRAME_F( 0 ) +#define RISCV_INTERRUPT_FRAME_FT1 RISCV_INTERRUPT_FRAME_F( 1 ) +#define RISCV_INTERRUPT_FRAME_FT2 RISCV_INTERRUPT_FRAME_F( 2 ) +#define RISCV_INTERRUPT_FRAME_FT3 RISCV_INTERRUPT_FRAME_F( 3 ) +#define RISCV_INTERRUPT_FRAME_FT4 RISCV_INTERRUPT_FRAME_F( 4 ) +#define RISCV_INTERRUPT_FRAME_FT5 RISCV_INTERRUPT_FRAME_F( 5 ) +#define RISCV_INTERRUPT_FRAME_FT6 RISCV_INTERRUPT_FRAME_F( 6 ) +#define RISCV_INTERRUPT_FRAME_FT7 RISCV_INTERRUPT_FRAME_F( 7 ) +#define RISCV_INTERRUPT_FRAME_FT8 RISCV_INTERRUPT_FRAME_F( 8 ) +#define RISCV_INTERRUPT_FRAME_FT9 RISCV_INTERRUPT_FRAME_F( 9 ) +#define RISCV_INTERRUPT_FRAME_FT10 RISCV_INTERRUPT_FRAME_F( 10 ) +#define RISCV_INTERRUPT_FRAME_FT11 RISCV_INTERRUPT_FRAME_F( 11 ) +#define RISCV_INTERRUPT_FRAME_FA0 RISCV_INTERRUPT_FRAME_F( 12 ) +#define RISCV_INTERRUPT_FRAME_FA1 RISCV_INTERRUPT_FRAME_F( 13 ) +#define RISCV_INTERRUPT_FRAME_FA2 RISCV_INTERRUPT_FRAME_F( 14 ) +#define RISCV_INTERRUPT_FRAME_FA3 RISCV_INTERRUPT_FRAME_F( 15 ) +#define RISCV_INTERRUPT_FRAME_FA4 RISCV_INTERRUPT_FRAME_F( 16 ) +#define RISCV_INTERRUPT_FRAME_FA5 RISCV_INTERRUPT_FRAME_F( 17 ) +#define RISCV_INTERRUPT_FRAME_FA6 RISCV_INTERRUPT_FRAME_F( 18 ) +#define RISCV_INTERRUPT_FRAME_FA7 RISCV_INTERRUPT_FRAME_F( 19 ) + +#endif /* __riscv_flen */ + #ifndef ASM #ifdef __cplusplus @@ -151,6 +259,29 @@ typedef struct { uintptr_t t4; uintptr_t t5; uintptr_t t6; +#if __riscv_flen > 0 + uint32_t fcsr; + RISCV_Float ft0; + RISCV_Float ft1; + RISCV_Float ft2; + RISCV_Float ft3; + RISCV_Float ft4; + RISCV_Float ft5; + RISCV_Float ft6; + RISCV_Float ft7; + RISCV_Float ft8; + RISCV_Float ft9; + RISCV_Float ft10; + RISCV_Float ft11; + RISCV_Float fa0; + RISCV_Float fa1; + RISCV_Float fa2; + RISCV_Float fa3; + RISCV_Float fa4; + RISCV_Float fa5; + RISCV_Float fa6; + RISCV_Float fa7; +#endif uintptr_t a0; uintptr_t a1; } RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame; |